HAMMERCORES Search Results

cordic algorithm

Abstract: CORDIC altera
Contextual Info: HammerCores by Altera White Paper CORDIC Functions CDPP & CDPS Introduction The two HammerCores by Altera CORDIC macros, CDPP and CDPS, use the CORDIC algorithm to convert rectangular to polar coordinates. This algorithm is also known as the backwards rotation CORDIC algorithm. The

sha1 hash

Abstract: A999 10K50S-1
Contextual Info: HammerCores by Altera White Paper SHA-1 Hash Function Introduction The Hammercores by Altera SHA-1 hash function implements the SHA-1 message-digest algorithm, as described in ® FIPS PUB 180-1, and is optimized for Altera FLEX 10KE and APEX 20K devices.

decryption

Contextual Info: HammerCores by Altera White Paper High-Speed Rijndael Encryption/Decryption Processors Introduction The Hammercores by Altera high-speed Rijndael encryption/decryption processors are optimized for Altera APEX 20K devices. The current versions of the high-speed cores support block lengths of 128 bits and key lengths of 128 bits only. Two

3nco

Contextual Info: HammerCores by Altera White Paper NCO Core Introduction Numerically Controlled Oscillators NCO are found in many applications, such as demodulation, frequency synthesis, and up/down conversion. The NCO core is fully parameterized, allowing you to optimize the NCO for

Multiplexor 64 inputs

Abstract: decryption DES Encryption FEDCBA9876543210 FDB975121FCA8642 52e478ea965166db 01A7CAF1C9613B84
Contextual Info: HammerCores by Altera White Paper DES Cores Introduction The HammerCores by Altera library of DES encryption and decryption cores consists of: DES encryption core DES decryption core DES encryption/decryption core control bit selectable The cores are compact – 450 to 600 Logic Cells (LCs), and high performance – up to 125 Mbps The cores

matlab code using 64 point radix 8

Abstract: radix-2 1345-2 radix fht 100
Contextual Info: HammerCores by Altera White Paper Hadamard Transform Processor Introduction ® The Hammercores by Altera Hadamard Transform Processor core is optimized for the Altera FLEX 10KE, ACEX 1K, and APEX 20K device families. The core is parameterizable and can support a wide range of transform

6L6GA

Abstract: branch metric return to zero decoder Viterbi Decoder viterbi decoder soft bit 10K30E viterbi
Contextual Info: HammerCores by Altera White Paper Viterbi Decoders Introduction The Hammercores by Altera high performance, soft decision Viterbi decoder cores are optimized for Altera ® TM FLEX 6000, FLEX 10K and APEX 20K devices. They are user parameterized to implement any number of

EPF10K30ETC144-1

Abstract: EPF10K50ETC144-1 EPF20K EP20K100E EP20K60E EPF10K100EQC208-1
Contextual Info: White Paper Area Optimized Soft Decision Viterbi Decoder Functions Introduction The Altera® area optimized, soft decision Viterbi decoder HammerCores are optimized for APEX 20K, FLEX®10K and FLEX 6000 devices. You can parameterize the devices by implementing any number of standard decoders or you

EPF10K10LC84-3

Abstract: compander companders application notes on Companding
Contextual Info: HammerCores by Altera White Paper u-Law Companders and A-Law Companders Introduction The HammerCores by Altera u-Law and A-Law Compander macros are very efficient, high performance, ® ® full precision voice telephony macros. They are optimized for Altera FLEX 6000, FLEX 8000, and FLEX

Hammercores

Abstract: EPF10K10A
Contextual Info: HammerCores by Altera White Paper Arctan Function Introduction The arctan function is based on the Hammercores by Altera CORDIC function. It has the ability to accept 4 quadrant input data in cartesian form, and returns a 4 quadrant arctangent. The macro can operate as a combinatorial single cycle function, or a pipelined function. When pipelined, the macro

Contextual Info: HammerCores by Altera White Paper MD5A Hash Function Introduction The Hammercores by Altera MD5 hash function implements the RSAMD5 message-digest algorithm, and is ® optimized for Altera FLEX 10KE and APEX 20K devices. The MD5 algorithm generates a 128-bit message-digest, or hash function, of an arbitrary length input, and is used for

8B10B

Abstract: 2D212
Contextual Info: HammerCores by Altera White Paper 8b/10b Encoders Introduction The 8b/10b encoders and decoders are used for physical layer coding for Gigabit Ethernet IEEE 802.3 , Fibre Channel, and other applications. The 8b/10b encoder takes byte inputs, and generates a DC balanced stream (equal

EE core

Contextual Info: HammerCores by Altera White Paper Low-Speed Rijndael Encryption/Decryption Processors Introduction The Hammercores by Altera low-speed Rijndael encryption/decryption processors implement the Rijndael ® encryption or decryption algorithms, and are optimized for Altera FLEX 10KE and APEX 20K devices.

EPM9560RC304-15

Abstract: EPM7064SLC44-10 vhdl code for ARQ EASY 21653 EPC1 price epc1213 EPM5064 EPM7032S through hole chip carriers Lexra PLMQ7192/256-160NC
Contextual Info: Newsletter for Altera Customers ◆ Fourth Quarter ◆ November 1998 Quartus: Altera’s Fourth-Generation Development Tool With Altera’s new QuartusTM software, programmable logic development tools enter the multi-million-gate era. This powerful fourthgeneration software meets

"Constant fraction discriminator"

Abstract: cti pet Constant fraction discriminator SIEMENS BST vhdl cordic code EPC1064V HP 30 pin lcd flex cable pinout vhdl code for cordic Constant fraction timing discriminator EPF10K50EQI240-2
Contextual Info: & News Views First Quarter, February 2000 The Programmable Solutions Company Newsletter for Altera Customers Altera Provides World-Class HDL Synthesis & Simulation Tools Altera has entered into agreements with Synopsys, Inc., and Mentor Graphics Corporation that enable Altera’s entire

synchronizer megafunction

Abstract: 8251 uart vhdl Viterbi Trellis Decoder texas ac685 A-AN-073-01 uart with fir filters UART 8251 vhdl implementation of 2-d discrete wavelet transform convolutional interleaver max plus flex 7000
Contextual Info: メガファンクション・ セレクタ・ガイド February 1998 トータル・ソリューションを提供する メガファンクション プログラマブル・ロジック・デバイス（P L D ）の集積度は 250,000 ゲートにも達するようになりディジタル・システム

CRC matlab

Abstract: mini project simulink QAM matlab OFDM Matlab code altera CORDIC ip vhdl code for ofdm vhdl code CRC CORDIC QAM modulation vhdl code for qam VHDL code for dac
Contextual Info: 信号処理用 IPメガファンクション System-on-a-Programmable-Chipデザインに対応した 信号処理ソリューション 信号処理用 IP：幅広いファンクション群が 検証ずみの性能を提供 リューションを実現するときに必要となるすべての機能が含ま

lEXRA lx5280

Abstract: Inventra M8051 Warp lx5280 8259 Programmable Interrupt Controller microcontroller 8052 m8051 warp gsm coding for 8051 microcontroller dvb-RCS internet Arasan interfacing 8051 with 300 GSM Modem datasheet
Contextual Info: Intellectual Property Selector Guide IP Building Blocks for System-on-a-ProgrammableChip Solutions March 2001 Contents 2 Introduction to Altera Megafunctions 4 Signal Processing Megafunctions 7 Communications Megafunctions 10 PCI & Other Bus Interface Megafunctions

GSM 900 simulink matlab

Abstract: verilog code for ofdm transmitter fir filter coding for gui in matlab digital IIR Filter VHDL code digital IIR Filter verilog code qpsk modulation VHDL CODE vhdl code for ofdm transmitter vhdl code for ofdm turbo codes qam system matlab code qpsk demapper VHDL CODE
Contextual Info: Signal Processing IP Megafunctions Signal Processing Solutions for System-on-a Programmable-Chip Designs May 2001 Signal Processing IP: Proven Performance in One Portfolio performance, high-throughput signal coding schemes, W processing algorithms. ireless and digital signal processing DSP

verilog code for 8 bit carry look ahead adder

Abstract: EPM7128 EPLD verilog code for lms adaptive equalizer Embedded Programming using the 8051 and Jam Byte lms algorithm using vhdl code altera EPM7032S EPF10K200E epf10k50v EPF6024AQI208-3 EP20K400
Contextual Info: Newsletter for Altera Customers ◆ First Quarter ◆ February 1999 FLEX 10KE Devices Meet the 66-MHz/64-Bit PCI Compliance Challenge The Altera FLEX® 10KE family meets the 66-MHz/64-bit peripheral component interconnect PCI compliance challenge. Flexibility and density