HB08 Search Results

HB08

Abstract: Custom Connector 5 pin male header
Contextual Info: HB SERIES ELECTRONIC PACKAGING PRODUCTS DESCRIPTION CONSTRUCTION 8 and 11 Pin Octal Style Male Headers Molding Pins • • High Temperature Phenolic Brass, Bright Tin Plated ORDERING CODE PART NO. DESCRIPTION HB08 HB11 HMS-1 8 Pin Octal Style Male Header Fig. 1

Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT08 . . . J OR W PACKAGE SN74AHCT08 . . . D, DB, DGV, N, NS,

ahct08

Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237K – OCTOBER 1995 – REVISED SEPTEMBER 2002 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT08 . . . J OR W PACKAGE SN74AHCT08 . . . D, DB, DGV, N, NS,

HB08Q

Abstract: AEC-Q100 Q100 SN74AHCT08Q SN74AHCT08QDRQ1 SN74AHCT08QPWRQ1 SN74AHCT08Q-Q1
Contextual Info: SN74AHCT08Q-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SGDS021 – FEBRUARY 2002 D D D D D D D D OR PW PACKAGE TOP VIEW Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With

RASH

Contextual Info: Foxconn Non-Shrouded Headers HB/HC Sériés Performance Characteristics: Break Away Header .025" 0.64mm Square Posts Electrical Characteristics P/N Description Insulation Resistance: 5000 M iiM in Dielectric Withstanding Voltage: 1000V AC Min at Sea Level

Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L − OCTOBER 1995 − REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible D Latch-Up Performance Exceeds 250 mA Per D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

Contextual Info: SN74AHCT08QĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SGDS021A − FEBRUARY 2002 − REVISED APRIL 2008 D OR PW PACKAGE TOP VIEW D Qualified for Automotive Applications D EPIC (Enhanced-Performance Implanted CMOS) Process 1A 1B 1Y 2A 2B 2Y GND D Inputs Are TTL-Voltage Compatible

Contextual Info: SN74AHCT08Q-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SGDS021 – FEBRUARY 2002 D D D D D D D D OR PW PACKAGE TOP VIEW Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With

Contextual Info: SN74AHCT08QĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SGDS021A − FEBRUARY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D EPIC Enhanced-Performance Implanted D OR PW PACKAGE (TOP VIEW CMOS) Process 1A 1B 1Y 2A 2B 2Y GND D Inputs Are TTL-Voltage Compatible

Contextual Info: Kintex-7 FPGA KC724 GTX Transceiver Characterization Board User Guide UG932 v2.1 December 13, 2013 The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

SN74AHCT08DR

Abstract: SN74AHCT08PWR
Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L − OCTOBER 1995 − REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible D Latch-Up Performance Exceeds 250 mA Per D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

ba39 regulator

Abstract: al15 schematic
Contextual Info: VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board User Guide UG957 v1.2 December 18, 2013 DISCLAIMER The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

VITA-57

Contextual Info: FMC XM101 LVDS QSE Card User Guide UG538 v1.1 September 24, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

Contextual Info: SN74AHCT08Q-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SGDS021 – FEBRUARY 2002 D D D D D D D D OR PW PACKAGE TOP VIEW Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With

SN74AHCT08QDRG4Q1

Abstract: SN74AHCT08Q SN74AHCT08QDRQ1 SN74AHCT08QPWRG4Q1 SN74AHCT08QPWRQ1
Contextual Info: SN74AHCT08QĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SGDS021A − FEBRUARY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D EPIC Enhanced-Performance Implanted D OR PW PACKAGE (TOP VIEW CMOS) Process 1A 1B 1Y 2A 2B 2Y GND D Inputs Are TTL-Voltage Compatible

AHCT08

Abstract: C101 SN54AHCT08 SN74AHCT08 A115-A
Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT08 . . . J OR W PACKAGE SN74AHCT08 . . . D, DB, DGV, N, NS,

AHct08

Abstract: SN74AHCT08DR SN74AHCT08PWR
Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L − OCTOBER 1995 − REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible D Latch-Up Performance Exceeds 250 mA Per D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

A115-A

Abstract: AHCT08 C101 SN54AHCT08 SN74AHCT08 HB08
Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT08 . . . J OR W PACKAGE SN74AHCT08 . . . D, DB, DGV, N, NS,

Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT08 . . . J OR W PACKAGE SN74AHCT08 . . . D, DB, DGV, N, NS,

Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L − OCTOBER 1995 − REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible D Latch-Up Performance Exceeds 250 mA Per D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

ti hb08

Abstract: SN74AHCT08DR SN74AHCT08PWR
Contextual Info: SN54AHCT08, SN74AHCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS237L − OCTOBER 1995 − REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible D Latch-Up Performance Exceeds 250 mA Per D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

Contextual Info: SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide UG751 v1.1 September 15, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

PTD08D021W

Abstract: MT8JTF12864HZ-1G6G1 LVCMOS18 M88E1111 ADV7511KSTZ virtex 5 lcd display controller Marvell alaska 88E1111 ba37 diode
Contextual Info: VC707 Evaluation Board for the Virtex-7 FPGA User Guide UG885 v1.4 May 12, 2014 The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

VITA-57

Contextual Info: DEMO MANUAL DC1525A LTC2175-14/-12, LTC2174-14/-12, LTC2173-14/-12, LTC2172-14/-12, LTC2171-14/-12, LTC2170-14/-12 12-Bit/14-Bit, 25Msps to 125Msps Quad ADCs DESCRIPTION Demonstration circuit 1525A supports a family of 14-Bit/12-Bit 25Msps to 125Msps ADCs. Each assembly features one of the following devices: LTC 2175-14,