I1995 Search Results

28f200-bB

Abstract: mt2f2 28F200-T L99 marking T199S
Contextual Info: PRELIMINARY M IC R O MT28F200 128K x 16, 256K x 8 FLASH MEMORY N 128K x 16, 256K x 8 FLASH MEMORY FEATURES PIN ASSIGNMENT (Top View • Five erase blocks: 16K B /8 K -w o rd bo o t b lo ck (protected) T w o 8 K B /4 K -w o rd p a ra m e ter b lo ck s T w o m ain m em o ry b lo ck s

Contextual Info: PRELIMINARY M T2LSYT3272T1/T2, M T4LSY6472T1/T2 32K. 64K X 72 S Y N C H R O N O U S SRAM M ODULE I^ IIC R O N SYNCHRONOUS SRAM MODULE 3 2 K, 64K x 72 SRAM 256KB/512KB, 3.3V, FLOW-THROUGH SYNCHRONOUS BURST, SECONDARY CACHE MODULES FEATURES PIN ASSIGNMENT Front View

Contextual Info: M T 4 C 4 0 0 1 J S 1 MEG x 4 DRAM |U|(=RON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (M T4C4001J) or 128ms (M T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process

M16H5

Contextual Info: . 1 1— » - « w . 1 DRAM M E G x 1 6 B U R S MT4LC1M16H5 T E D D R A M 1 MEG x 16 3.3V, BURST EDO FEATURES PIN ASSIGNMENT Top View • B u rst ord er, interleav e o r linear, p ro g ra m m ed by execu tin g W C B R cy cle a fter initializatio n • Sin g le +3 .3 V ± 5 % p o w e r sup ply