ICE40 Search Results

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.9, April 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features  Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.5, August 2013 iCE40 LP/HX Family Data Sheet Introduction August 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.4, July 2013 iCE40 LP/HX Family Data Sheet Introduction July 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device  Flexible Logic Architecture

Contextual Info: iCEdragon Demo Board User’s Guide November 2012 EB80_01.0 iCEdragon Demo Board Introduction Thank you for choosing the iCEdragon Demo Board. This board is designed to help you develop hardware solutions based on the Android OS using the iCE40™ ultra-low density FGPA.

LATTICE SEMICONDUCTOR Tape and Reel Specification

Abstract: LVDS25E 0.4mm pitch BGA routing ICE40 FPGA pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm
Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.3, May 2013 iCE40 LP/HX Family Data Sheet Introduction April 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device  Flexible Logic Architecture

Contextual Info: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family March 22, 2012 1.3 Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features  LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power 35 µA at f =0 kHz (Typical)

n25q32

Contextual Info: iCEstick Evaluation Kit User’s Guide August 2013 EB82_01.0 iCEstick Evaluation Kit Introduction Thank you for choosing the Lattice Semiconductor iCEstick Evaluation Kit. This guide describes how to start using the iCEstick Evaluation Kit, an easy-to-use USB form factor board for rapidly prototyping designs using the iCE40 FPGA. Along with the evaluation board, this kit includes a pre-loaded

LATTICE SEMICONDUCTOR Tape and Reel Specification

Contextual Info: iCE40LM Family Data Sheet DS1045 Version 1.4, August 2014 iCE40LM Family Data Sheet Introduction January 2014 Data Sheet DS1045 General Description iCE40LM family is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as

8x816

Abstract: DS1048
Contextual Info: iCE40 Ultra Family Data Sheet Preliminary DS1048 Version 1.3, July 2014 iCE40 Ultra Family Data Sheet Introduction July 2014 Preliminary Data Sheet DS1048 General Description iCE40 Ultra family is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. The iCE40 Ultra family includes integrated SPI and I2C

Contextual Info: iCE40LM Family Data Sheet DS1045 Version 1.2, March 2014 iCE40LM Family Data Sheet Introduction January 2014 Data Sheet DS1045 General Description iCE40LM family is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as

Contextual Info: iCE40 HX-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue December 15, 2011 1.1 Preliminary Data Sheet Figure 1: iCE40 HX-Series Family Architectural Features  HX-Series - Tablet targeted series optimized for high performance Low cost package offerings

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.6, September 2013 iCE40 LP/HX Family Data Sheet Introduction August 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device

ICE40 lattice

Abstract: ICE40 FPGA 0.4mm pitch BGA routing TN1251 ICE40LP1K ICE40LP1K-CM36 GDDR71 pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm ICE40LP384SG32
Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.2, April 2013 iCE40 LP/HX Family Data Sheet Introduction April 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device  Flexible Logic Architecture

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.7, October 2013 iCE40 LP/HX Family Data Sheet Introduction October 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device

DP-24-B

Abstract: 04/DP02A F5/LIN VHDL source code
Contextual Info: iCE40HX-8K Breakout Board User’s Guide November 2013 EB85_01.0 iCE40HX-8K Breakout Board Introduction Thank you for choosing the Lattice iCE40HX-8K Breakout Board. This document provides technical information and instructions for using the iCE40HX-8K Breakout Board. This kit

LSM330DLC application note

Abstract: TSSOP34338
Contextual Info: iCE40LM4K Sensor Evaluation Kit User’s Guide January 2014 EB83_01.0 iCE40LM4K Sensor Evaluation Kit Introduction Thank you for choosing the Lattice iCE40LM4K Sensor Evaluation Kit. This guide describes how to begin using the iCE40LM4K Sensor Evaluation Kit, an easy-to-use platform for rapidly prototyping system control designs using an

ICE40 FPGA

Abstract: ICE40LP1K-CM121 ICE40LP1K ice40lp 225ba ICE40LP1K-CM36 ICE40
Contextual Info: iCE40 LP Series Ultra Low-Power FPGA Family October 03, 2012 1.32 Figure 1: iCE40 LP-Series Family Architectural Features LP-Series - optimized for low power Ultra-small footprints Proven, high-volume 40 nm, low-power CMOS technology I/O Bank 0 I/O Bank 1

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 3.0, July 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features  Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode

ice40lp

Abstract: ICE40 FPGA sublvds to lvds lp1k BGA 81 ball
Contextual Info: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family March 30, 2012 1.31 Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features  LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power 35 µA at f =0 kHz (Typical)

ultra fine pitch BGA

Abstract: HX640 BGA Package 14x14 ICE40 lattice sub-lvds ICE40 FPGA 132-BA
Contextual Info: iCE40 HX-Series Ultra Low-Power mobileFPGA™ Family March 30, 2012 1.31 Data Sheet Figure 1: iCE40 HX-Series Family Architectural Features  HX-Series - Tablet targeted series optimized for high performance Low cost package offerings 80% faster than iCE65

25p10av

Abstract: PMOD12 25P10 od3 Voltage Regulator arduino Example capacitive touch ADP2140ACPZ3312R7 DSC101 ICE40HX1K-VQ100 2140ACP
Contextual Info:  iCEblink40 iCE40HX1K Evaluation Kit User’s Guide May 2012 Revision: EB73_01.0  iCEblink40 iCE40HX1K Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor iCEblink 40 HX1K Evaluation Kit. This guide describes how to begin using the iCEblink40 Evaluation Kit, an easy-to-use platform for rapidly prototyping designs using the iCE40 mobileFPGA™.

siliconblue

Abstract: ice40lp 245KB sublvds lvds ICE65 sub-lvds iCE40LP8K-CM225 ICE40LP1K
Contextual Info: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue December 15, 2011 1.1 Preliminary Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features  LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power

BANK05

Abstract: 12x12 bga thermal resistance DP23A ICE40 FPGA siliconblue sub-lvds
Contextual Info: iCE40 HX-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue July 11, 2011 0.91 Preliminary Data Sheet Figure 1: iCE40 HX-Series Family Architectural Features  HX-Series - Tablet targeted series optimized for high performance Low cost package offerings

Contextual Info: iCE40LM Family Data Sheet DS1045 Version 1.3, March 2014 iCE40LM Family Data Sheet Introduction January 2014 Data Sheet DS1045 General Description iCE40LM family is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as