Contextual Info: R iCE Socket Adapter SiliconBlue iCEsabVQ100-01 September 13, 2010 1.2 Data Sheet Figure 1: iCEsabVQ100-01  Supports NVCM programming of iCE65 mobileFPGA devices  Programming NVCM in iCE65 device using iCEcable and iCEprog  Compatible Tools:  iCEcableM100-01

Contextual Info: R iCE65 Ultra Low-Power mobileFPGA™ Family SiliconBlue November 12, 2009 2.0.1 Data Sheet Figure 1: iCE65 Family Architectural Features  First high-density, ultra low-power singlechip, SRAM mobileFPGA family specifically designed for hand-held applications and

Contextual Info: R iCE Socket Adapter SiliconBlue iCEsabCB284-01 September 13, 2010 1.2 Data Sheet Figure 1: iCEsabCB284-01  Supports NVCM programming of iCE65 mobileFPGA devices  Programming NVCM in iCE65 device using iCEcable and iCEprog  Compatible Tools:  iCEcableM100-01

Contextual Info: iCE40 HX-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue December 15, 2011 1.1 Preliminary Data Sheet Figure 1: iCE40 HX-Series Family Architectural Features  HX-Series - Tablet targeted series optimized for high performance Low cost package offerings

Contextual Info: R DiePlus Advantage iCE65L08F-TCS110I SiliconBlue November 24, 2010 1.0 Preliminary Data Sheet Supplement New package Supplement for CS110 4.35mm x 4.77 mm WLCSP (see iCE65 L-Series Data Sheet for Electrical and Architecture Characteristics) Figure 1: iCE65L08 WLCSP

siliconblue

Abstract: ice40lp 245KB sublvds lvds ICE65 sub-lvds iCE40LP8K-CM225 ICE40LP1K
Contextual Info: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue December 15, 2011 1.1 Preliminary Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features  LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power

BANK05

Abstract: 12x12 bga thermal resistance DP23A ICE40 FPGA siliconblue sub-lvds
Contextual Info: iCE40 HX-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue July 11, 2011 0.91 Preliminary Data Sheet Figure 1: iCE40 HX-Series Family Architectural Features  HX-Series - Tablet targeted series optimized for high performance Low cost package offerings

Contextual Info: R iCE Socket Adapter SiliconBlue iCEsabCB121-01 September 13, 2010 1.0 Data Sheet Figure 1: iCEsabCB121-01  Supports NVCM programming of iCE65 mobileFPGA devices  Programming NVCM in iCE65 device using iCEcable and iCEprog  Compatible Tools:  iCEcableM100-01

Contextual Info: R iCE Socket Adapter SiliconBlue iCEsabCB81-01 September 13, 2010 1.0 Data Sheet Figure 1: iCEsabCB81-01  Supports NVCM programming of iCE65 mobileFPGA devices  Programming NVCM in iCE65 device using iCEcable and iCEprog  Compatible Tools:  iCEcableM100-01

Contextual Info: R DiePlus Advantage SiliconBlue January 25, 2011 2.0.6 Data Sheet DiePlus Advantage is SiliconBlue’s focused program to provide designers with an optimal device mounting solution for mobile handheld applications. This data sheet provides detailed information regarding DiePlus

sublvds lvds

Abstract: siliconblue DP13A ST 80500 transistor ICE65
Contextual Info: iCE65 P-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue April 22, 2011 1.31 Data Sheet Figure 1: iCE65P P-Series Family Architectural Features  High-density, ultra low-power single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and

ICE65L04F

Abstract: sublvds lvds 65L02 Y20150 38448 337 BGA footprint mini din pcb mount 442-665 7475 D flip-flop ice65l04
Contextual Info: Handheld iCE: iCE65 Ultra Low-Power Programmable Logic Family R SiliconBlue March 25, 2009 1.4.4 Preliminary (SUBJECT TO CHANGE) First high-density, ultra low-power programmable logic family specifically designed for hand-held applications and long battery life

Contextual Info: R iCEprog SiliconBlue iCEprogM1050-01 August 06, 2010 1.1 Data Sheet Figure 1: iCEprogM1050-01  Supports NVCM programming of iCE65 mobileFPGA devices  Programming NVCM in iCE65 device using iCEcable  Compatible Tools:      

Contextual Info: R iCEcable SiliconBlue iCEcableM100-01 August 06, 2010 1.1 Data Sheet Figure 1: iCEcableM100-01  Supports configuration and programming of iCE65 mobileFPGA devices  Configuration of iCE65 devices, master or slave  Programming NVCM in iCE65 device

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.5, August 2013 iCE40 LP/HX Family Data Sheet Introduction August 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.4, July 2013 iCE40 LP/HX Family Data Sheet Introduction July 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device  Flexible Logic Architecture

PMOD12

Contextual Info:  iCEblink40-LP1K Evaluation Kit User’s Guide September 2012 Revision: EB75_01.1  iCEblink40-LP1K Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor iCEblink40 -LP1K Evaluation Kit. This guide describes how to begin using the iCEblink40-LP1K Evaluation Kit, an easy-to-use platform for rapidly

addersubtractor

Abstract: adder-subtractor design isplever 2.0 release note, ispvm
Contextual Info: LatticeMico Timer The LatticeMico timer is a highly configurable countdown timer with a WISHBONE-compliant slave interface compatible with the LatticeMico32 microprocessor. Version This document describes the 3.0 version formerly the 7.0 SP2 version of the

LatticeMico32

Contextual Info: LatticeMico GPIO The LatticeMico GPIO is a general-purpose input/output core that provides a memory-mapped interface between a WISHBONE slave port and generalpurpose I/O ports. The I/O ports can connect to either on-chip or off-chip logic. Version This document describes the 3.4 version of the LatticeMico GPIO.

wishbone

Abstract: Supercool siliconblue memory_passthru
Contextual Info: LatticeMico Memory Passthrough The LatticeMico memory passthrough provides a data path between the internal WISHBONE bus and the external WISHBONE memory devices. Version This document describes the 3.0 version of the LatticeMico memory passthrough. Functional Description

ICE40 lattice

Abstract: ispLEVER classic 1.2 memory controller ICE40 FPGA wishbone
Contextual Info: LatticeMico Dual-Port On-Chip Memory Controller The LatticeMico dual-port on-chip memory controller provides two slave interfaces to the WISHBONE bus master ports that allow the ports to access the Lattice Semiconductor FPGA embedded block RAMs EBRs . The

Contextual Info: LatticeMico EFB for MachXO2 The LatticeMico EFB for MachXO2 is a hard architectural block that is known as the Embedded Function Block EFB . The EFB includes a Serial Peripheral Interface (SPI), two I2Cs, and a timer/counter peripheral. All of these hard IP

ICE65

Abstract: siliconblue aardvark i2c
Contextual Info: Silicon Blue Technology Corporation 3255 Scott Blvd, Suite 101 Santa Clara, CA 95054 USA www.siliconbluetech.com 09-00156-00 User’s Manual iCEprogM1050 , iCEcableM100 and SAB-XXXXX-X V 1.2 Silicon Blue Technology Corporation 3255 Scott Blvd, Suite 101 Santa Clara, CA 95054 USA

LATTICE SEMICONDUCTOR Tape and Reel Specification

Abstract: LVDS25E 0.4mm pitch BGA routing ICE40 FPGA pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm
Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.3, May 2013 iCE40 LP/HX Family Data Sheet Introduction April 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device  Flexible Logic Architecture