Untitled
Abstract: No abstract text available
Text: R iCE Socket Adapter SiliconBlue iCEsabVQ100-01 September 13, 2010 1.2 Data Sheet Figure 1: iCEsabVQ100-01 Supports NVCM programming of iCE65 mobileFPGA devices Programming NVCM in iCE65 device using iCEcable and iCEprog Compatible Tools: iCEcableM100-01
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iCEsabVQ100-01
iCE65
iCE65
iCEcableM100-01
iCEprogM1050-01
40-pin
VQ100
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Untitled
Abstract: No abstract text available
Text: R iCE65 Ultra Low-Power mobileFPGA™ Family SiliconBlue November 12, 2009 2.0.1 Data Sheet Figure 1: iCE65 Family Architectural Features First high-density, ultra low-power singlechip, SRAM mobileFPGA family specifically designed for hand-held applications and
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iCE65
12-NOV-2009)
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Untitled
Abstract: No abstract text available
Text: R iCE Socket Adapter SiliconBlue iCEsabCB284-01 September 13, 2010 1.2 Data Sheet Figure 1: iCEsabCB284-01 Supports NVCM programming of iCE65 mobileFPGA devices Programming NVCM in iCE65 device using iCEcable and iCEprog Compatible Tools: iCEcableM100-01
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iCEsabCB284-01
iCE65
iCE65
iCEcableM100-01
iCEprogM1050-01
40-pin
CB132/196
CB284
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Untitled
Abstract: No abstract text available
Text: iCE40 HX-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue December 15, 2011 1.1 Preliminary Data Sheet Figure 1: iCE40 HX-Series Family Architectural Features HX-Series - Tablet targeted series optimized for high performance Low cost package offerings
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iCE40â
iCE40
iCE65
iCEman40HX
iCE40HX
15-DEC-2011)
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Untitled
Abstract: No abstract text available
Text: R DiePlus Advantage iCE65L08F-TCS110I SiliconBlue November 24, 2010 1.0 Preliminary Data Sheet Supplement New package Supplement for CS110 4.35mm x 4.77 mm WLCSP (see iCE65 L-Series Data Sheet for Electrical and Architecture Characteristics) Figure 1: iCE65L08 WLCSP
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iCE65L08F-TCS110I
CS110
iCE65
iCE65L08
CS110
24-NOV-2010)
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siliconblue
Abstract: ice40lp 245KB sublvds lvds ICE65 sub-lvds iCE40LP8K-CM225 ICE40LP1K
Text: iCE40 LP Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue December 15, 2011 1.1 Preliminary Data Sheet Figure 1: iCE40 LP-Series Family Architectural Features LP-Series - Smartphone targeted series Programmable Logic Block (PLB) optimized for low power
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iCE40TM
iCE65
iCE40
15-DEC-2011)
siliconblue
ice40lp
245KB
sublvds lvds
sub-lvds
iCE40LP8K-CM225
ICE40LP1K
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BANK05
Abstract: 12x12 bga thermal resistance DP23A ICE40 FPGA siliconblue sub-lvds
Text: iCE40 HX-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue July 11, 2011 0.91 Preliminary Data Sheet Figure 1: iCE40 HX-Series Family Architectural Features HX-Series - Tablet targeted series optimized for high performance Low cost package offerings
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iCE40TM
iCE65
iCE40
11-JUL-2011)
BANK05
12x12 bga thermal resistance
DP23A
ICE40 FPGA
siliconblue
sub-lvds
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Untitled
Abstract: No abstract text available
Text: R iCE Socket Adapter SiliconBlue iCEsabCB121-01 September 13, 2010 1.0 Data Sheet Figure 1: iCEsabCB121-01 Supports NVCM programming of iCE65 mobileFPGA devices Programming NVCM in iCE65 device using iCEcable and iCEprog Compatible Tools: iCEcableM100-01
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iCEsabCB121-01
iCE65
iCE65
iCEcableM100-01
iCEprogM1050-01
40-pin
CB121
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Untitled
Abstract: No abstract text available
Text: R iCE Socket Adapter SiliconBlue iCEsabCB81-01 September 13, 2010 1.0 Data Sheet Figure 1: iCEsabCB81-01 Supports NVCM programming of iCE65 mobileFPGA devices Programming NVCM in iCE65 device using iCEcable and iCEprog Compatible Tools: iCEcableM100-01
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iCEsabCB81-01
iCE65
iCE65
iCEcableM100-01
iCEprogM1050-01
40-pin
13-SEP-2010)
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Untitled
Abstract: No abstract text available
Text: R DiePlus Advantage SiliconBlue January 25, 2011 2.0.6 Data Sheet DiePlus Advantage is SiliconBlue’s focused program to provide designers with an optimal device mounting solution for mobile handheld applications. This data sheet provides detailed information regarding DiePlus
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iCE65
iCE65L04
25-JAN-2011)
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sublvds lvds
Abstract: siliconblue DP13A ST 80500 transistor ICE65
Text: iCE65 P-Series Ultra Low-Power mobileFPGA™ Family R SiliconBlue April 22, 2011 1.31 Data Sheet Figure 1: iCE65P P-Series Family Architectural Features High-density, ultra low-power single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and
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iCE65TM
iCE65P
22-APR-2011)
sublvds lvds
siliconblue
DP13A
ST 80500 transistor
ICE65
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ICE65L04F
Abstract: sublvds lvds 65L02 Y20150 38448 337 BGA footprint mini din pcb mount 442-665 7475 D flip-flop ice65l04
Text: Handheld iCE: iCE65 Ultra Low-Power Programmable Logic Family R SiliconBlue March 25, 2009 1.4.4 Preliminary (SUBJECT TO CHANGE) First high-density, ultra low-power programmable logic family specifically designed for hand-held applications and long battery life
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iCE65TM
iCE65
25-MAR-2009)
ICE65L04F
sublvds lvds
65L02
Y20150
38448
337 BGA footprint
mini din pcb mount
442-665
7475 D flip-flop
ice65l04
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Untitled
Abstract: No abstract text available
Text: R iCEprog SiliconBlue iCEprogM1050-01 August 06, 2010 1.1 Data Sheet Figure 1: iCEprogM1050-01 Supports NVCM programming of iCE65 mobileFPGA devices Programming NVCM in iCE65 device using iCEcable Compatible Tools:
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iCEprogM1050-01
iCE65
iCE65
iCEcableM100-01
iCEsabQN84-01,
iCEsabVQ100-01,
VQ100
iCEsabCB132/196-01,
CB132/196
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Untitled
Abstract: No abstract text available
Text: R iCEcable SiliconBlue iCEcableM100-01 August 06, 2010 1.1 Data Sheet Figure 1: iCEcableM100-01 Supports configuration and programming of iCE65 mobileFPGA devices Configuration of iCE65 devices, master or slave Programming NVCM in iCE65 device
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iCEcableM100-01
iCE65
iCEprogM1050-01
iCEsabQN84-01,
iCEsabVQ100-01,
VQ100
iCEsabCB132/196-01,
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Untitled
Abstract: No abstract text available
Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.5, August 2013 iCE40 LP/HX Family Data Sheet Introduction August 2013 Data Sheet DS1040 Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device
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iCE40â
DS1040
iCE40
DS1040
Distribut2013
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Untitled
Abstract: No abstract text available
Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.4, July 2013 iCE40 LP/HX Family Data Sheet Introduction July 2013 Data Sheet DS1040 Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device Flexible Logic Architecture
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iCE40â
DS1040
iCE40
DS1040
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PMOD12
Abstract: No abstract text available
Text: iCEblink40-LP1K Evaluation Kit User’s Guide September 2012 Revision: EB75_01.1 iCEblink40-LP1K Evaluation Kit User’s Guide Introduction Thank you for choosing the Lattice Semiconductor iCEblink40 -LP1K Evaluation Kit. This guide describes how to begin using the iCEblink40-LP1K Evaluation Kit, an easy-to-use platform for rapidly
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iCEblink40-LP1K
iCEblink40â
iCE40â
iCE40LP1K
iCE40LP1K-QN84
iCE40
PMOD12
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addersubtractor
Abstract: adder-subtractor design isplever 2.0 release note, ispvm
Text: LatticeMico Timer The LatticeMico timer is a highly configurable countdown timer with a WISHBONE-compliant slave interface compatible with the LatticeMico32 microprocessor. Version This document describes the 3.0 version formerly the 7.0 SP2 version of the
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LatticeMico32
addersubtractor
adder-subtractor design
isplever 2.0 release note, ispvm
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LatticeMico32
Abstract: No abstract text available
Text: LatticeMico GPIO The LatticeMico GPIO is a general-purpose input/output core that provides a memory-mapped interface between a WISHBONE slave port and generalpurpose I/O ports. The I/O ports can connect to either on-chip or off-chip logic. Version This document describes the 3.4 version of the LatticeMico GPIO.
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wishbone
Abstract: Supercool siliconblue memory_passthru
Text: LatticeMico Memory Passthrough The LatticeMico memory passthrough provides a data path between the internal WISHBONE bus and the external WISHBONE memory devices. Version This document describes the 3.0 version of the LatticeMico memory passthrough. Functional Description
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ICE40 lattice
Abstract: ispLEVER classic 1.2 memory controller ICE40 FPGA wishbone
Text: LatticeMico Dual-Port On-Chip Memory Controller The LatticeMico dual-port on-chip memory controller provides two slave interfaces to the WISHBONE bus master ports that allow the ports to access the Lattice Semiconductor FPGA embedded block RAMs EBRs . The
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Abstract: No abstract text available
Text: LatticeMico EFB for MachXO2 The LatticeMico EFB for MachXO2 is a hard architectural block that is known as the Embedded Function Block EFB . The EFB includes a Serial Peripheral Interface (SPI), two I2Cs, and a timer/counter peripheral. All of these hard IP
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ICE65
Abstract: siliconblue aardvark i2c
Text: Silicon Blue Technology Corporation 3255 Scott Blvd, Suite 101 Santa Clara, CA 95054 USA www.siliconbluetech.com 09-00156-00 User’s Manual iCEprogM1050 , iCEcableM100 and SAB-XXXXX-X V 1.2 Silicon Blue Technology Corporation 3255 Scott Blvd, Suite 101 Santa Clara, CA 95054 USA
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iCEprogM1050
iCEcableM100
iCE65
10MHz
siliconblue
aardvark i2c
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LATTICE SEMICONDUCTOR Tape and Reel Specification
Abstract: LVDS25E 0.4mm pitch BGA routing ICE40 FPGA pitch 0.4mm BGA 0.4mm pitch 2.5x2.5mm
Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.3, May 2013 iCE40 LP/HX Family Data Sheet Introduction April 2013 Data Sheet DS1040 Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device Flexible Logic Architecture
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iCE40TM
DS1040
iCE40
DS1040
LATTICE SEMICONDUCTOR Tape and Reel Specification
LVDS25E
0.4mm pitch BGA routing
ICE40 FPGA
pitch 0.4mm BGA
0.4mm pitch 2.5x2.5mm
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