IC 74LS 121 Search Results

SN54LS440

Abstract: SN54LS442 SN54LS444 SN74LS440 SN74LS442 SN74LS444
Contextual Info: SN 54LS440 THRU S N 54LS 442, SN54LS444 SN74LS440 THRU S N 74LS 442, SN 74LS444 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS SDLS176 • 3 -W a y A s y n c h ro n o u s C o m m u n ic a tio n □ 2 4 2 5 , A U G U S T 1 9 7 9 -R E V IS E D M AR C H 1 9 8 8 S N 54L S ' . . . J PACKAGE

TTL IC 74LS244

Abstract: 74LS244 Motorola 74LS 74ls244 as buffer 74LS241
Contextual Info: M MOTOROLA OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN 54/74LS 240, 241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board

Y12t

Abstract: 74LS375N
Contextual Info: Signetics 74LS375 Latch Quad Bistable Latch Product Specification Logic Products FEATURES T Y P IC A L P R O P A G A TIO N D E LA Y TY PE • Quad transparent latch • Complementary outputs 7 4LS 375 12 T Y P IC A L S U PP LY C U R R E N T T O T A L ns

74221

Abstract: 1N3064 1N916 74LS N74221D N74221N
Contextual Info: 74221 Signetics Multivibrator Dual Monostable Multivibrator Product Specification Logic Products FEATURES • Pulse width variance is typically less than ±0.5% for 98% of the units • The '221 demonstrates electrical and switching characteristics that are virtually identical to the '121

74LS465

Abstract: 74ls gate symbols IC 74LS 121 74ls467
Contextual Info: TYPES SN54LS465 THRU SN54LS468, SN74LS465 THRU SN74LS468 OCTAL BUFFERS WITH 3-STATE OUTPUTS D 2 6 3 1 , J A N U A R Y 1981 - R E V I S E D D E C E M B E R 198 3 M echanically and Functionally Interchange­ able W ith D M 7 1 /8 1 L S 9 5 th ru D M 7 1 /8 1 L S 9 8

Contextual Info: 74S350 Signelics Shifter 4-Bit Shifter With 3-State Outputs Product Specification Logic Products FEATURES • Shifts 4 bits of data to 0, 1, 2, 3 places under control of two select lines • 3-State outputs for bus organized systems TY PE T Y P IC A L PR O P A G A TIO N

Contextual Info: Signetics 74S350 Shifter 4-Bit Shifter With 3-State Outputs Product Specification Logic Products FEATURES • Shifts 4 bits of data to 0, 1, 2, 3 places under control of two select lines • 3-State outputs for bus organized systems TYPE TYPICAL PROPAGATION

74S64

Abstract: logic symbol 74S logic symbol 74S64
Contextual Info: 74S64 Signetics Gate Four-Two-Three-Two-Input AND-OR-Invert Gate Product Specification Logic Products TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 3.5ns 8mA 74S64 ORDERING CODE COMMERCIAL RANGE V cc = 5 V ± 5 % ; Ta = 0°C »0 +70°C PACKAGES

ic 74 138 DECODER

Abstract: 74LS138P 74LS138PC
Contextual Info: NATIONAL SEHICOND -CLOGIO 02E » | bS01122 0Db^ ^ J j D^ D IA G R A M P IN O U T A T- 66-21-55 54S/74S138 54LS/74LS138 Ao T l i l Vcc 1-OF-8 DECO DER/DEM ULTIPLEXER Al [ 7 H JO o A2 [ 7 Ei [T 13]S2 rad jJJ03 T7|04 33 os E3[6 ö?|T T ]0 6 g n d (7 D E S C R I P T IO N — T he ’ 138 is a high speed 1-of-8 decoder/dem ultiplexer.

LS689

Abstract: d2617 16D06 LS688 SN54LS682 SN54LS689 SN74LS689 sn74ls682
Contextual Info: TYPES SN54LS682 THRU SN54LS689, SN74LS682THRU SN74LS689 8-BIT MAGNITUDE/IDENTITY COMPARATORS D2617, JANUARY 1981-REVJSED DECEMBER 1983 Compares T w o 8-B it Words Choice o f Totem -Pole or Open-Collector Outputs S N 5 4 L S 6 8 2 TH R U S N 5 4 L S 6 8 5 . . . J PACKAGE

74LS series logic gate symbols

Abstract: ly2j IC 74LS 121 SN74LSS40 54LS240
Contextual Info: TYPES SN74LS540, SN74LS541, SN54LS540, SN54LS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 0 2 5 4 6 . A U G U S T 197 9 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers R EV IS E D A P R IL 198 5 SN54LSS40, SN54LS541 . J P A C K A G E

DM54LS165J

Abstract: DM54LS165W DM74LS165 DM74LS165N DM74LS165WM J16A M16B N16E W16A
Contextual Info: EM ICONDUCTQ R t DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description This device is an 8-bit serial shift register w hich shifts data in the direction of Q A tow ard Q H w hen clocked. Parallel-in ac­ cess is m ade available by eight individual direct d ata inputs,

74LS165N

Abstract: 54LS165J
Contextual Info: EM ICONDUCTQ R t DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description This device is an 8-bit serial sh ift register w hich shifts data in the direction of Q A tow ard Q H w hen clocked. Parallel-in ac­ cess is m ade available by eight individual direct d ata inputs,

Contextual Info: I R C H I L D S E M IC O N D U C T O R T M DM74LS251 3-STATE Data Selectors/Multiplexers Features • 3-STATE version o f LS151 To m inim ize the possibility th a t tw o outputs will a ttem pt to take a com m on bus to opposite logic levels, th e output con­

74LS443

Abstract: 74LS448 IC TA 31101 74LS441 diagram CD 5265 cs
Contextual Info: TYPES SN54LS440 THRU SN54LS444, SN54LS448 SN74LS440 THRU SN74LS444, SN74LS448 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS D2425, AU G U ST 1979 3-W ay Asynchronous Com m unication S N 54LS ' . . . J PACKAGE S N 74LS ' . . . D W , J OR N PACKAG E On-C hip Bus Selection Decoding

74LS194AN

Abstract: LS194
Contextual Info: + E M IC D N D U C T D R t DM74LS194A 4-Bit Bidirectional Universal Shift Register This bidirectional shift register is designed to incorporate v ir­ tually all o f the features a system designer m ay w an t in a shift register; they feature parallel inputs, parallel outputs,

5 to 32 decoder using 4 t0 16 decoders

Abstract: LSI38 sn54138 LS138 SN54LS138 SN54S138 SN74LS138 SN74S138A
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S13BA 3-LINE TO 8 LINE DECODERS/DEMULTIPLEXERS SDLS014 DECEMBER T9 7 2 — REVISED M A R C H 198 8 • Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems • 3 Enable Inputs to Simplify Cascading

74LS366AN

Abstract: 74LS36
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74LS366A Hex 3-STATE Inverting Buffer This device contains six independent gates each o f which perform s an inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low

LS645-1

Abstract: LS645 Sn 04 diod a7 diod DIOD B4 74ls645
Contextual Info: 8 -B it Buffer Transceivers S N 5 4 /7 4 L S 6 4 5 SN74LS645-1 Ordering Information Features/ Benefits • Three-stale outputs drive bus lines • Low current PNP inputs reduce loading • Symmetric — equal driving capability in each direction • 20-pin SKINNYDIP saves space

Contextual Info: S E M IC O N D U C T O R tm DM74LS670 3-STATE 4-by-4 Register Files and the read tim e 24 ns typical . The register file has a non-volatile readout in that data is not lost w hen addressed. General Description These register files are organized as 4 w ords of 4 bits each,

Contextual Info: y MN2020 DIGITALLY CONTROLLED PROGRAMMABLE-GAIN AMPLIFIER MICRO NETWORKS DESCRIPTION • Programmable Gain 1 to 128 in 8 Steps • Gain Selected with a 3-Bit TTL Word • Excellent Gain Accuracy: ±0.002% @ G=1 ±0.1% @ G=128 • Low Offset Voltage Drift ± 5/iV/°C

74LS157N

Abstract: 74LS158N 74LS157M M74LS157N 74ls158
Contextual Info: S E M IC O N D U C T O R tm DM74LS157/DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers • S ource program m able counters General Description These d ata selectors/m ultiplexers contain inverters and d riv­ ers to supply full on-chip d ata selection to the four output

74LS109AN

Abstract: 12111 74ls109am
Contextual Info: I R C H I I - D EM I C O N D U C T O R T General Description This device contains tw o independent positive-edge-triggered J-K flip-flops w ith com plem entary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a v o lt­

Contextual Info: SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244, SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS A PRIL 1985 —R EVISED MARCH 1988 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers