IC ACT10 Search Results
IC ACT10 Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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SCL3400-D01-004 | Murata Manufacturing Co Ltd | 2-axis (XY) digital inclinometer |
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SCC433T-K03-PCB | Murata Manufacturing Co Ltd | 2-Axis Gyro, 3-axis Accelerometer combination sensor on Evaluation Board |
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D1U54T-M-2500-12-HB4C | Murata Manufacturing Co Ltd | 2.5KW 54MM AC/DC 12V WITH 12VDC STBY BACK TO FRONT AIR |
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SCC433T-K03-10 | Murata Manufacturing Co Ltd | 2-Axis Gyro, 3-axis Accelerometer combination sensor |
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SCC433T-K03-004 | Murata Manufacturing Co Ltd | 2-Axis Gyro, 3-axis Accelerometer combination sensor |
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IC ACT10 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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ULC EPM5128
Abstract: 85C090 EP1200 epm5130 XC3020 PAL18P8 PLS163 XC2018 PLHS153 PLS100
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GAL16V8 PAL16P8 PAL18P8 PAAAL16L8 PAL10L8 PAL14L4 PAL16L2 PAL16RP8 PAL16RP4 PAL16R8 ULC EPM5128 85C090 EP1200 epm5130 XC3020 PLS163 XC2018 PLHS153 PLS100 | |
Contextual Info: s e m ic o n d u c t o r Revised November 1999 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two_ high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock |
OCR Scan |
74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 | |
rca 1967
Abstract: 74AC112
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CD54/74AC109, CD54/74AC1à CD54/74ACT109, CD54/74ACT112 SCHS282 92cs-3sà CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC109 rca 1967 74AC112 | |
schematic diagram atx Power supply 500w
Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
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P462-ND P463-ND LNG295LFCP2U LNG395MFTP5U US2011) schematic diagram atx Power supply 500w pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS | |
GR-1244-CORE
Abstract: 5MHz OCXO Stratum 3 Synchronizer SDH 209 12.800MHZ IC1 723 N13T1 T4 560 B 5 to 32 decoder using 4 t0 16 decoders CHIP DIODE m7
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DS3100 DS3100 GR1244, GR-253, GR-1244-CORE 5MHz OCXO Stratum 3 Synchronizer SDH 209 12.800MHZ IC1 723 N13T1 T4 560 B 5 to 32 decoder using 4 t0 16 decoders CHIP DIODE m7 | |
Contextual Info: DS3100 Stratum 3/3E Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers |
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DS3100 DS3100 GR1244, GR-253, | |
IC 7106Contextual Info: DS3100 Stratum 3/3E Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers |
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DS3100 GR1244, GR-253, freq64) IC 7106 | |
IC 7108
Abstract: IC 7106 TCXO 24.576 0.1uF, 63V 2-pin ir receiver 5MHz OCXO GR-1244-CORE Datasheet, Circuit Cross Refer ACS8520 ACS8530 DS3100
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DS3100 DS3100 GR1244, GR-253, var224 IC 7108 IC 7106 TCXO 24.576 0.1uF, 63V 2-pin ir receiver 5MHz OCXO GR-1244-CORE Datasheet, Circuit Cross Refer ACS8520 ACS8530 | |
IC 7106
Abstract: IC 714 ssmf ACS8520 ACS8530 DS3100 DS3100GN GR-1244 GR-253 18Hz
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DS3100 DS3100 GR1244, GR-253, IC 7106 IC 714 ssmf ACS8520 ACS8530 DS3100GN GR-1244 GR-253 18Hz | |
Contextual Info: Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S282 IS- » 2 1JÎK IC f*ÎR • 3 4 1 1 • IO Dual “J-K” Flip-Flop with Set and Reset F /F 1 CD54/74AC/ACT109 - Positive-Edge-Triggered J, K |
OCR Scan |
CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CS-36532 CD54/74AC109 | |
ACS8520
Abstract: ACS8530 DS3100 DS3101 DS3101GN GR-1244 GR-253 ocxo 25MHz GR378
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DS3101 DS3101 GR-1244, GR-253, ACS8520 ACS8530 DS3100 DS3101GN GR-1244 GR-253 ocxo 25MHz GR378 | |
JRC 45600
Abstract: YD 803 SGS 45600 JRC TDA 7277 TDA 5072 krp power source sps 6360 2904 JRC Sony SHA T90 SA philips HFE 4541
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OCR Scan |
ZOP033 ZOP035 ZOP036 ZOP037 ZOP038 ZOP039 ZOP045 ZOP042 ZOP041 ZOP043 JRC 45600 YD 803 SGS 45600 JRC TDA 7277 TDA 5072 krp power source sps 6360 2904 JRC Sony SHA T90 SA philips HFE 4541 | |
ic1232Contextual Info: PRELIMINARY DATASHEET + DS3100 Stratum 3/3E Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multi-protocol BITS/SSU |
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DS3100 DS3100 GR1244, GR-253, ic1232 | |
SA8FContextual Info: Data Sheet April 2012 DS3100 Stratum 2/3E/3 Timing Card IC General Description When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers |
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DS3100 GR1244, GR-253, SA8F | |
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amp 4546
Abstract: ssmf 34.368Mhz e2 e3 8448 RESREF amp 4546 jc ACS8520 ACS8530 DS3100 DS3100GN GR-1244
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DS3100 DS3100 GR1244, GR-253, 166ns amp 4546 ssmf 34.368Mhz e2 e3 8448 RESREF amp 4546 jc ACS8520 ACS8530 DS3100GN GR-1244 | |
IC 7106
Abstract: IC1 723 N13T1 I431 telcordia
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DS3100 GR1244, GR-253, IC 7106 IC1 723 N13T1 I431 telcordia | |
Contextual Info: DEMO KIT AVAILABLE DS3100 Stratum 3/3E Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers |
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DS3100 DS3100 GR1244, GR-253, | |
Contextual Info: DEMO KIT AVAILABLE DS3101 Stratum 3/3E Timing Card IC www.maxim-ic.com FEATURES GENERAL DESCRIPTION When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements. With 14 input clocks, the device directly |
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DS3101 DS3101 GR-1244, GR-253, | |
Ic 7423Contextual Info: DEMO KIT AVAILABLE DS3101 Stratum 3/3E Timing Card IC www.maxim-ic.com FEATURES GENERAL DESCRIPTION When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements. With 14 input clocks, the device directly |
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DS3101 GR-1244, GR-253, Ic 7423 | |
Contextual Info: ADVANCE M IC R O N MT41 LC256K32D4 S 256K x 32 SGRAM 1 SYNCHRONOUS GRAPHICS RAM 256K x 32 SGRAM PULSED RAS, DUAL BANK, PIPELINED, 3.3V OPERATION FEATURES • Fully synchronous; all signals registered on positive edge of system dock • Internal pipelined operation; column address can be |
OCR Scan |
LC256K32D4 024-cyde | |
Contextual Info: i t ic i i c u n o .i v i u i i u a y , r v u ^ u o i i v , 1 9 0 c Revision: Monday, December 14,1992 m< PRELIMINARY WJs CYPRESS SEMICONDUCTOR • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies |
OCR Scan |
84-pin 16-bit | |
CD54AC109
Abstract: CD54AC112 CD54ACT109 CD54ACT112
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CD54AC109/3A CD54ACT109/3A CD54AC109 CD54ACT109 CD54AC/ACT109 16-lead CD54AC112/3A CD54ACT112/3 CD54AC112 CD54ACT112 | |
Contextual Info: 17E High-Reliability Advanced CMOS Logic IC s_ Recent Additions CD54AC109/3A CD54ACT109/3A D • 3075001 0024=177 0 G E S0LI1 STATE —i— i n 1 T 4b-ö7 •O / Dual “J-K” Flip-Flop with Set and Reset Positlve-Edge-Triggered J, K) The RCA CD54AC109 and CD54ACT109 are dual “J-K” flipflops with set and reset that utilize the new RCA ADVANCED |
OCR Scan |
CD54AC109/3A CD54ACT109/3A CD54AC109 CD54ACT109 CD54AC/ACT109 16-lead | |
Contextual Info: M MOTOROLA M C 74A C 10 M C 74A C T 10 T rip le 3 -In p u t N A N D G ate TRIPLE 3 -IN P U T N A N D G ATE • Outputs Source/Sink 24 mA • 'ACT10 Has TTL Compatible Inputs N SUFFIX CASE 646-06 PLASTIC 1 D SUFFIX CASE 751A-02 PLASTIC M A X IM U M R A T IN G S * |
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ACT10 51A-02 MC74AC10 MC74ACT10 74ACT |