ICT 20 PIN PLCC Search Results

Contextual Info: September 1994 Commercial Preliminary INC. PEEL 20V8 -15/-25 CMOS Programmable Electrically Erasable Logic Features Compatible with Popular 20V8 Devices — 20V8 socket and function compatible — Programs with standard 20V8 JEDEC file — 24-pin DIP/SOIC, 28-pin PLCC packages

Contextual Info: Commercial/ Industrial INC. TM PA7140 PEEL Array Programmable Electrically Erasable Logic Array Features I CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP and 44-pin PLCC packages I Versatile Logic Array Architecture - 24 l/Os, 14 inputs, 60 registers/latches

am29ma16

Abstract: AM29M16 AM29M16 PLD atmel 404 93c46 29f512 gal18v8 ATMEL 24C32A COP8622C atmel 93C46 AT27040
Contextual Info: Ironwood Electronics Programming Adapters PR.1 Programming Adapters allow the programming of PROM, PLD, EPROM, EEPROM or PAL devices on programmers or ATE equipment with DIP sockets. We support PLCC, LCC, PGA, SOIC including TSOP , FP, BGA and QFP packages.

Contextual Info: ¡ET Preliminary Commercial INC. PEEL 20V8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Features Compatible with Popular 20V8 Devices — 20V8 socket and function compatible — Programs with standard 20V8 JEDEC file — 24-pin DIP/SOIC, 28-pin PLCC packages

Contextual Info: Commercial/Industrial PA7572 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches

Contextual Info: Commercial/Industrial PA7572 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches

TLO 81

Abstract: 16009A ICT Peel 26V12 PA7536 ma706
Contextual Info: Commercial/Industrial PA7536 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC and PLCC packages Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches

Contextual Info: July, 1994 INC. Commercial PA7128 PEEL Array Programmable Electrically Erasable Logic Array Features • CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC, and PLCC packages ■ High-Speed, Moderate Power Consumption - As fast as 9ns/15ns tpdi/tpdx , 83.3MHz fmax

Contextual Info: July, 1994 Industrial PA7128I PEEL Array Programmable Electrically Erasable Logic Array Features • Industrial Grade Specifications - Vcc = 4.5V to 5.5V, TA = -40 to +85°C - Reprogrammable 28-pin DIP, SOIC, and 28-pin PLCC packages ■ High-Speed, Moderate Power Consumption

Contextual Info: July, 1994 INC. Commercial PA7140 PEEL Array Programmable Electrically Erasable Logic Array Features • CMOS Electrically Erasable Technology ■ High-Speed, Moderate Power Consumption - Reprogrammable in 40-pin DIP and 44-pin PLCC packages - As fast as 13ns/20ns tpdi/tpd , 66.6MHz fmax

ICT Peel

Abstract: PA7572
Contextual Info: Commercial/Industrial PA7572 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features

Contextual Info: Industrial INC. TM PA7024I PEEL Array Programmable Electrically Erasable Logic Array Features • Industrial Grade Specifications I High-Speed, Moderate Power Consumption - Vcc = 4.5V to 5.5V, TA = -40°C to +85°C - Reprogrammable 24-pin DIP, SOIC, and 28-pin PLCC packages

Contextual Info: July, 1994 INC. Industrial TM PA7128I PEEL Array Programmable Electrically Erasable Logic Array Features I Industrial Grade Specifications - Vcc = 4.5V to 5.5V, TA = -40 to +85=C - Reprogrammable 28-pin DIP, SOIC, and 28-pin PLCC packages • High-Speed, Moderate Power Consumption

Contextual Info: September 1994 Preliminary Commercial INC. PEEL 22CV8 -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Low Power Alternative to Standard PLDs — Lower power than quarter-power PALs and GALs — 10mA typical/15mA maximum power CMOS Electrically Erasable Technology

Contextual Info: l ^ = • INC. PEEL 16V8 Data Sheet October 1994 4Ô4G7Q7 00014b5 ^50 ■ [ [U Advanced Designation The "Advanced” designation on an ICT data sheet indicates that the product is not yet ready for release. The specifications are subject to change, are based on design goals or preliminary part evaluation, and

PEEL22V10AZ

Contextual Info: September 1994 Preliminary Commercial INC. TM . PEEL 22V10AZ -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Ultra Low Power — Ice = 25p.A typical at standby — Icc = 3.5mA (typical) at 1MHz — tpD = 15ns and 25ns versions • Architectural Flexibility

"Programmable Electrically Erasable Logic Array"

Abstract: PA7024P-15 TLC 555 EP610 GAL6002 LCC14 PA7024 PA7024J-15 EP610 ORDERING ICT 20 PIN PLCC
Contextual Info: Commercial/ Industrial PA7024 PA7024 PEELTM Array Programmable Electrically Erasable Logic Array Features • CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages -Optional JN package for 22V10 power/ground compatibility

7024S15

Contextual Info: Commercial/ Industrial INC. TM PA7024 PEEL Array Programmable Electrically Erasable Logic Array Features I CMOS Electrically Erasable Technology I High-Speed Commercial and Industrial Versions - Reprogrammable in 24-pin DIP, SOIC, and 28-pin PLCC packages

22CV10AP

Abstract: 22cv10 nte quick cross ict peel 18CV8J palce programmer schematic blackjack vhdl code PA7140J-20 INTEL PLD910 PALCE610
Contextual Info: Data Book General Information PEEL Arrays PEEL Devices Special Products and Services Development Tools Application Notes and Reports Package Information PLACE Users Manual_ Introduction to PLACE PLACE Installation Getting Started with PLACE Operation Reference Guide

TLC 555

Abstract: ICT Peel
Contextual Info: Commercial/ Industrial INC. PA7128 PEEL Array Programmable Electrically Erasable Logic Array Features CMOS Electrically Erasable Technology High-Speed Commercial and Industrial Versions - Reprogrammable in 28-pin DIP, SOIC and PLCC packages - As fast as 9ns/15ns tpdi/tpdx , 83.3M Hz (fMAX)

Contextual Info: Preliminary Commercial PEEL 18LV8Z-25 CMOS Programmable Electrically Erasable Logic Device FEATURES • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc =25 uA typical at standby - Icc = 2 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

Contextual Info: Commercial INC. TM PA7128 PEEL Array Programmable Electrically Erasable Logic Array Features I CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC, and PLCC packages I High-Speed, Moderate Power Consumption - As fast as 9ns/15ns tpdi/tpdx , 76.9MHz fmax

Contextual Info: Preliminary Commercial IN C . PEEL 22CV1 OAZ -15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 133 product term x 44 input AND array — Up to 22 inputs and 10 I/O pins — 12 possible macrocell configurations

Contextual Info: Commercial/ Industrial INC. TM PA7128 PEEL Array Programmable Electrically Erasable Logic Array Features • CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC, and PLCC packages I Versatile Logic Array Architecture - 12 l/Os, 14 inputs, 36 registers/latches