IEEE1596.3 Search Results

DS90LV019

Abstract: DS90LV019TM DS90LV019TMTC EIA-644 IEEE1596 M14A MTC14
Contextual Info: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DS90LV019 は EIA-644 及び IEEE1596.3 SCI LVDS 規格に適 合しておりこのデバイスを 2 個使用することにより1 対 1 の低消 費、高速 100Mbps 以上 (50MHz) の全二重のデジタル伝送が構

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • • • • • • • • The PI90LVB010 is a differential line driver and receiver transceiver that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA644LVDS standards, the difference is that the driver output current

IEEE1596

Abstract: PI90LVB010 PI90LVB010U PI90LVB010UE PI90LVB010W PI90LVB010WE
Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • • • • • • • • The PI90LVB010 is a differential line driver and receiver transceiver that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA644LVDS standards, the difference is that the driver output current

IEEE1596.3

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • Bus LVDS Signaling BLVDS The PI90LVB010 is a differential line driver and receiver (transceiver) that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA• Designed for Double Termination Applications

IEEE1596.3

Abstract: IEEE1596 10MF 35V IEEE-1596 DS90LV018A DS90LV031A EIA-422 EIA-644 M08A ds90
Contextual Info: • ■ ■ ■ ■ ■ ■ ■ DS90LV018A は EIA-644 および IEEE1596.3 SCI LVDS 規格 に適合しており同規格の LVDS のドライバと組み合わせると 1 対 1 の低消費電力、高速 400Mbps (200MHz) 以上のデジタル 伝送が構成できます。

IEEE1596

Abstract: PI90LVB010 PI90LVB010UE PI90LVB010WE
Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • • • • • • • • The PI90LVB010 is a differential line driver and receiver transceiver that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA644LVDS standards, the difference is that the driver output current

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • Bus LVDS Signaling BLVDS The PI90LVB010 is a differential line driver and receiver (transceiver) that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA• Designed for Double Termination Applications

DS3100

Abstract: DS3105 DS3105LN GR-1244-CORE GR-253-CORE LQFP64 MCR10 ACS8525 MCR10 ROHS D1801
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing

DB01P

Abstract: DCI circuit diagram
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET AD9739 SYNC_OUT SYNC_IN LVDS DDR RECEIVER I120 CLK DISTRIBUTION DIV-BY-4 SYNCCONTROLLER TxDAC CORE IOUTP IOUTN DACCLK 07851-001 DCO VREF DLL (MU CONTROLLER) Broadband communications systems Military jammers Instrumentation, automatic test equipment

nx10 alarm system

Abstract: nx10 alarm
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3102 is a highly integrated central timing and

DS26C31

Abstract: IEEE1596.3 DS90C401 DS90C402 EIA-422 EIA-644 IEEE1596 5K10 tia 250v
Contextual Info: DS90C401 LVDS 2 回路入り CMOS 差動出力ライン・ドライバ 概要 特長 DS90C401は平衡伝送ラインでのデジタル・データ伝送用に設計され た Low Voltage Differential Signaling LVDS 形態の 2 回路入り CMOS 差動出力のライン・ドライバです。D S 9 0 C 4 0 1 は E I A - 6 4 4 及び

d 9329

Abstract: trc 9500 8755 interfacing chip pin diagram of ic 7489 agilent 8762 22253d IC TA 7089 P 74344 IT 8755 E j 5804 f11
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION DIV-BY-4 IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems

PEC 4179 DIODE

Abstract: 327879-001US
Contextual Info: Intel Communications Chipset 89xx Series Datasheet October 2012 Order Number: 327879-001US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

IEEE1596

Abstract: PI90LV019 PI90LV019W PI90LVT019W 50ohm resistors 0201 DOUBLE DIFFERENTIAL BUS TRANSCEIVER LVB 1.32
Contextual Info: PI90LV019 PI90LVB019 PI90LVT019

nx62

Abstract: 2ic30
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3106 Line Card Timing IC www.maxim-ic.com FEATURES GENERAL DESCRIPTION Advanced DPLL Technology ƒ Programmable PLL bandwidth:18 Hz to 400 Hz ƒ Manual Reference Switching ƒ Holdover on Loss of Input Reference

temperature controller CHB 402

Abstract: c531 diode c528 transistor pair diodes C509 s401 diode C520 A/D ROHDE SCHWARZ SMHU smd diode S7 r433 l504
Contextual Info: Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC AD9219 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB to Nyquist ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.3 LSB (typical)

LM317 3.3v

Abstract: IEEE1596 IEEE1596.3-1996 LM317 LMH6555 LMV321 ADC08100 ADC081000 IEEE1596.3 IEEE-1596
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

842 317 SO8

Contextual Info: Intel Communications Chipset 89xx Series Datasheet June 2013 Order Number: 327879-002US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

IEEE1596

Contextual Info: 19-1534; Rev 1; 10/99 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator Features ♦ +3.3V Single Supply ♦ 1.45W Power Dissipation MAX3831 ♦ 4-Channel Mux/Demux with Fully Integrated 2.488GHz Clock Generator ♦ Frame Detection Maintains Channel Assignment

Contextual Info: ADVANCE INFORMATION PI90LVB010

asus motherboard circuit diagram

Abstract: SuperSpeed USB 3.0 to Serial ATA Bridge P1263 intel MOTHERBOARD SERVICE MANUAL
Contextual Info: Intel Atom Processor E3800 Product Family Datasheet October 2013 Revision 1.0 Reference Number: 538136 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

hsm2812

Abstract: ANSI-644 ADA4937-2 AN-835 TC1-1-13M IEEE-1596 TC1-1-13M equivalent murata LTE band pass filter
Contextual Info: 10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator AD9267 FEATURES AVDD PDWNB PDWNA DRVDD LVDS DRIVERS OR±A VIN+A Σ-Δ MODULATOR VIN–A D3±A D0±A PLL_LOCKED VREF CFILT AD9267 PLLMULT4 PLLMULT3 PLLMULT2 PHASELOCKED LOOP CLK+ CLK– DCO±

T3150

Contextual Info: Transcede 3xxx Wireless Base Station System on Chip Data Sheet 843xx-DSH-001-A October 2013 Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Contextual Info: 10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator AD9267 FUNCTIONAL BLOCK DIAGRAM FEATURES PDWNB PDWNA DRVDD LVDS DRIVERS OR±A VIN+A MODULATOR VIN–A D3±A D0±A PLL_LOCKED VREF CFILT AD9267 PLLMULT4 PLLMULT3 PLLMULT2 PHASELOCKED LOOP