IM BC Search Results

intersil im6100

Abstract: IM6654 512X8 24 PIN EPROM eprom 6653 J 6920 A IM6653 g 6653 4096-Bit UV Erasable PROM intersil eprom
Contextual Info: IM 6 6 5 3 /IM 6 6 5 4 4 0 9 6 Bit CMOS UV Erasable PROM INIERHL FEATURES GENERAL DESCRIPTION • O rganization — IM 6653: 1024 x 4 IM 6654: 5 1 2 x 8 • • Low Power — 770jiW M axim um Standby High Speed — 300ns 10V A ccess T im e for IM 6653/54 Al

Contextual Info: REV. UNLESS OTHERWISE NOTED DIMENSIONS ARE IN INCHES [MIUMETERS ARE IN BRACKETS] BC O N E P L A C E D E C IM A L S ± .1 [ 2 . 5 4 ] THREE PLAC E TWO P L A C E D E C IM A L S ± .0 1 [.2 5 ] FOUR TOLERANCES ARE: D E C IM A L S ± P L A C E D E C IM A L 5 ±

IMSH4GP12A1F1C

Contextual Info: May 2008 IM[S/H]H1GP03A1F1C IM[S/H]H2GP[13/02]A1F1C IM[S/H]H4GP[23/12]A1F1C 240-Pin DDR3 Registered Modules with Parity bit 1GByte, 2GByte and 4GByte EU RoHS Compliant Advance Internet Data Sheet Rev. 0.61 Advance Internet Data Sheet DDR3 Registered DIMM IM[S/H]H[1G/2G/4G]PxxA1F1C

Solitron J775-2

Abstract: BT196 SS14 TOSHIBA 1n5822 TOSHIBA SS550 BT127 SE140 NSR8140S NBS25-400 1N4007 toshiba
Contextual Info: CROSS REFERENCE INDUSTRIAL R u t No. 10D05 iœ i îœ i 10D2 1 302 im 1004 10D4 10D6 10 6 IO » im 11DQ03 11DQ04 11DQ05 11DQ06 15B4B41 15D4B41 15G4B41 15J4B41 1B4B42 im a im o naco in n o 1G4B42 lHi 117 1BB 1J4B42 1*1217 1*12171 1K1217B 1N1218 1K1218A 1*12188

MA03-2

Abstract: MA07 MA08 BU2134AK MA13 simple diagram for electronic clock MA04 - 2
Contextual Info: Communication ICs Gray scale processor 32 tones BU2134AK The BU2134AK is an LSI designed for use in im age scanners and facsim ile m achines, with a function w hich takes analog im age signals ou tput from an im age sensor in an im age processing device and converts them to binary fo r­

w2k transistor

Abstract: 570x BCM570X netxtreme 570X-WP100-R 10Lnk
Contextual Info: WHITE PAPER BCM570X Broadcom NetXtreme Gigabit Ethernet Teaming INTRODUCTION The Broadcom Advanced Server Program BASP is an intermediate (IM) driver that implements teaming functionality along with load balancing, fault tolerance, and VLAN tagging. The IM supports the following

qimonda ddr3

Contextual Info: January 2008 IM[S/H]H1GP03A1F1C IM[S/H]H2GP[13/02]A1F1C IM[S/H]H4GP[23/12]A1F1C 240-Pin DDR3 Registered Modules with Parity bit 1GByte, 2GByte and 4GByte RoHS compliant Advance Internet Data Sheet Rev. 0.51 Advance Internet Data Sheet DDR3 Registered DIMM

Intel 82072

Abstract: 82072A 82072 8272A Intel+82072 8272A block diagram 255D APX186 Intel 8272A iAPX 286
Contextual Info: ß ß s y iM iM A im r in t e i 82072 CHMOS HIGH INTEGRATION FLOPPY DISK CONTROLLER Programmable Drive Motor On/O ff Delays Addresses Up to 256 Tracks Directly, Supports Unlimited Tracks Integrated Analog Data Separator with Software Selectable Data Rates 250K,

Contextual Info: December 2008 IM[S/H]H1GP03A1F1C IM[S/H]H2GP[13/02]A1F1C IM[S/H]H4GP[23/12]A1F1C 240-Pin DDR3 Registered Modules with Parity bit 1-GByte, 2-GByte and 4-GByte EU RoHS Compliant Advance Internet Data Sheet Rev. 0.64 Advance Internet Data Sheet DDR3 Registered DIMM

IMSH4GP12A1F1C

Abstract: IMHH4GP12A1F1C IMHH2GP02A1F1C PC3 "cross reference" 92-100-B
Contextual Info: November 2008 IM[S/H]H1GP03A1F1C IM[S/H]H2GP[13/02]A1F1C IM[S/H]H4GP[23/12]A1F1C 240-Pin DDR3 Registered Modules with Parity bit 1-GByte, 2-GByte and 4-GByte EU RoHS Compliant Advance Internet Data Sheet Rev. 0.63 Advance Internet Data Sheet DDR3 Registered DIMM

SE82365SL

Abstract: SFH 6711 Lm 7011 Z365
Contextual Info: O K I Semiconductor Z36S PCM CIA 0.8|im T ech n olo gy M ega M acrocell DESCRIPTION The 2365 PCMCIA Mega Macrocell is a featured library element in OKI's 0.8|im Sea of Cates and 0.8|im Customer Structured Array families. The OKI implementation of the Mega Macrocell is fully compatible

Contextual Info: ZENER DIODES, GLASS PACKAGE, GENERAL PURPOSE 400mW N o m in a l Zener V o tu g e M a x im u m Zener im p e d a n t * Test a t I, C u rre n t M a x im u m R e v e r s e N o g «A V. JAaxirtturrt Zener C u r re n t lili 1. Max <mA| BC 0 Sum * B ,C ,D S u ffix

Contextual Info: M IM P5218 P 9-Line SCSI Terminator Plug and Play ISO 9001 Registered KEY FEATURES D E S C R IP T IO N T h e IM P 5218 term inator is part o f IM P 's SCSI term inator fam ily o f high-performance, adaptive, non-linear m ode SCSI products, which are designed

gal20v10

Abstract: 20f001n ycl 74LCX245DT 20F001N 93C46 smd ca91c860 HH-1M2012 HT6542B Realtek RTL8019AS RTL8019AS CARD
Contextual Info: R Y 7/98 WinCept Reference Design User’s Manual PR EL IM IN A CONTENTS Paragraph Number EL IM IN A R Y Overview .5 Information, Documentation, and

National Semiconductor IMP-8

Abstract: Benning TD19-2530-5-0-5-4 imp-16a Benning IMP-16A/521D
Contextual Info: P R E L IM IN A R Y I " - ' t" \ r r-k v. " I r / 1974 IM P -1 6 A /5 2 1 D , IM P -1 6 A /5 2 2 D , IM P -8 /5 2 0 D M O S /L S I control and read only memory unit C R O M D A T A : JULY ' ( ' g e n e ra l d e s c rip tio n The Control and Read Only Memory U nit (CROM)

SN74LS604

Contextual Info: SN54LS604, SN54LS606, SN54LS607, SN74LS604, SN74LS606, SN74LS607 OCTAL 2-INPUT MULTIPLEXED LATCHES D254-5, JULY 1979-REVISED MARCH 1988 T IM 9 9 6 0 4 , T IM 9 9 6 0 6 , T IM 9 9 6 0 7 SN 54LS 604, SN 54LS 606, SN 54LS607 . . JO PACKAGE SN 74LS 604, SN 74LS 606. SN 74LS607 . . . JD OR N PACKAGE

BS20

Abstract: BS30 S70L41B S-70L41B bs31 display 25B22
Contextual Info: Contents F eatu re s . Specifications . D im ension s 1 1 2 A bsolute M ax im u m R atings . 2 Pin Configuration 2 B L O C K D IA G R A M

Intersil BIPOLAR PROM PROGRAMMING SPECIFICATION

Abstract: Bipolar PROM programming BIPOLAR PROM PROGRAMMING SPECIFICATION IM5600CPE IM5600 PACKAGE IM5610CPE DM5600 IM5600CJE IM5610 intersil detailed bipolar prom programming
Contextual Info: IM 5 60 0/IM 5 61 0 2 5 6 B it B ipolar Read O nly Memory DMÜ^DIL FEATURES G EN ER A L D E S C R IP T IO N • Uses Patented A IM Programming Elem ent for — Superior Reliability — High Programming Yield — Fast Programming Speed < 1 sec — T T L Processing Com patibility

PB-IF-03

Abstract: 232C-LKS-adapter DSV401 contrans ts 11 FSK 9600 Profibus USB IC FFH1 interface abb variable frequency drive wiring diagram circuit diagram of smart home alarm system RS232 HART Modem circuit diagram
Contextual Info: DSV401 R3 SMART VISION Device Management Tool for Intelligent Field Instruments User Manual IM/DSV401 ABB Device Management Tool DSV401 R3(SMART VISION) User Manual Doc.-No. IM/DSV401 Issued: 12.05 Manufacturer: ABB Automation Products GmbH Schillerstr. 72

54HC

Abstract: 74HC M54HC42 M74HC42 function of 74LS42 IC
Contextual Info: HS-CMOS INTEGRATED CIRCUITS •I I I P R E L IM IN A R Y D A T A BCD-TO-DEC IM AL DECODER DESCRIPTION The M 54/74HC42 is a high speed CMOS BCD-TOD ECIM AL DECODER fabricated in silicon gale C2MOS technology. It has the same high speed perform ance of LSTTL

Contextual Info: Preliminary Information This docum ent contains inform ation on a new product. The param etric inform ation, although not fully characterized, is the result o f testing initial devices. Bt254 Distinguishing Features Applications Im age Processing Im age Capture

BFW 10 fet

Abstract: transistor bf 494 bf 494 transistor BFW 10 A FET transistor bf 184 transistor BF 253 transistor bf 241 BF 184 transistor transistor bf 495 transistor bf 254
Contextual Info: 6091788 MICRO ELECTRONICS CORP_ 820 00652 D J 3 /~>7 MICRO ELECTRONICS CORP 02 DE | bCH17fl0 DDDDbSS 1 V C E SA T CASE Pd (mVY) *C Im A) V 'c CEO (V) min max Im A l V CE (V) 167 — — — — 1 3 3 2.5 4 max 'c fT min Cob Cre* max N.F. (MHz)

2N5248

Abstract: BC264C 2N5557 2N5103 2N5485 2n5556 BF244A BF245C 2N5104 BC264A
Contextual Info: N -Channel Junction Field Effect Transistors GENERAL PURPOSE M A X IM U M R A T IN G S ' dss Im A l TYPE VG S off (V Y fs (mm hos) Ciss Crss NF (pF) (pF) (dB) max max max CASE NO. Pd (mW) b v gss (V) m in BC264A BC264E! BC264C BC264D TO-92DE TO-92DE TO-92DE

Contextual Info: Mate 5 with: S-SW SSO, SSM. BSW. ESW ESQ, CLH. BCS. IDS5 DSD NO. PINS PER ROW LEAD STYLE PLATING OPTION ROW L J o p t io n Features: 30u" 0,76|.im G o ld on p o s t, 200 u " (5,0B (im | Tin on ta il • Single or double row • Vertical or horizontal pin orientation