J3 IC Search Results

50MHZ

Contextual Info: S c h e m a t ic : E le c t r ic a l Isolation Voltage: S p e c if ic a t io n s : 1500Vac J1.J2 to (P1.P3) Isolation Voltage: 1500Vac (J3.J6) to (P4.P6) Turns Ratio: (PB-P5-F4):{J6-J3)=1,41 CT:1 CT±3% Turns Ratio: (P3-P2-P1):(J2-J1)=1CT:1CT±3% OCL: J3 -J6 : 350uH Min @100KHz 1D0mV SmADC

TE28F640J3C-120

Abstract: 28F64J3 28f256j3c SL894 RC28F128J3C-150 SL897 28F128j3c TE28F640J3C120 sl896 28F320J3C
Contextual Info: Intel StrataFlash Memory J3 256-Mbit J3 Family Specification Update June 2005 The 28F256J3, 28F128J3, 28F640J3, and 28F320J3 may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current

DP5Z1MM8NKH3

Abstract: 00FIH
Contextual Info: 1Mx8, 120 - 200ns, STACK/PGA 30A189-01 A 8 Megabit FLASH EEPROM DP5Z1MM8NKY/I3/H3/J3/DP5Z1MX8NKA3 PRELIMINARY DESCRIPTION: The DP5Z1MM8NKY/I3/H3/J3/DP5Z1MX8NKA3 ‘’SLCC’’ devices are a revolutionary new memory subsystem using Dense-Pac Microsystems’

DP5Z1MM16PH3

Abstract: DP5Z1MM16PI3 DP5Z1MM16PJ3 DP5Z1MM16PY DP5Z1MW16PA3
Contextual Info: 1Mx16, 120 - 200ns, STACK/PGA 30A162-21 A 16 Megabit FLASH EEPROM DP5Z1MM16PY/I3/H3/J3/DP5Z1MW16PA3 PRELIMINARY DESCRIPTION: The DP5Z1MM16PY/I3/H3/J3/DP5Z1MW16PA3 ‘’SLCC’’ devices are a revolutionary new memory subsystem using Dense-Pac Microsystems’

Contextual Info: LOWER ROW ELECTRICAL SPECIFICATIONS: OPERATING TEMPERATURE RANGE: 1.0 TURNS RATIO: P1 - P2 - P 3 : (J1 - J2 ) (P4 - P5 - P 6 ) : (J3 - J6 ) 2.0 INDUCTANCE: 3.0 LEAKAGE INDUCTANCE: 4.0 INTERWINDING CAPACITANCE: (P6,P5,P4) TO (J6 ,J3 ) (P3,P2,P1) TO (J2 ,J1 )

1117 S Transistor

Abstract: TOSHIBA bat Transistor b 1117
Contextual Info: TOSHIBA TENTATIVE GT5J311,GT5J311 SM TOSHIBA INSULATED GATE BIPOLAR TRANSISTOR G T5 J3 1 1 , SILICON N CHANNEL IGBT G T 5 J3 1 1 (S M ) Unit in mm HIGH POWER SWITCHING APPLICATIONS GT5J311 MOTOR CONTROL APPLICATIONS 10.3 MAX The 3rd Generation Enhancement-Mode

GT10J312

Abstract: CP20A
Contextual Info: GT10J312,GT10J312 SM TOSHIBA TOSHIBA INSULATED GATE BIPOLAR TRANSISTOR SILICON N CHANNEL IGBT G T 1 0 J3 1 2 , G T 1 0 J3 1 2 ( S M ) Unit in mm HIGH POWER SWITCHING APPLICATIONS GT10J312 MOTOR CONTROL APPLICATIONS 1.32 The 3rd Generation Enhancement-Mode

CD075014 2X5

Abstract: CD075014 ATTiny23V PL-326 atmel 0409 680R MBR0520L NC7SZ57P6X STK600 C4022
Contextual Info: 5 4 3 2 1 J1 and J2 goes down to the mother board. ATTiny23U / ATTiny43U Routing&Socket card SILK: USAGE: BOOST regulator: open Vtarget jumper on mainboard short J8 strap wire from mainboard Vtarget pin1 to J3 Vbat pin 1 w/o BOOST regulator short J3 (Vbat)

Contextual Info: ELECTRICAL SPECIFICATIONS: OPERATING TEMPERATURE RANGE: 1.0 INDUCTANCE: P 6-J6=P3-J3 2 .0 DC RESISTANCE: P 6 - J 6 P 3-J3 P 2-J2 P 1-J1 3.0 3.0 COMMON MODE ATTENUATION: FREQUENCY M H z ; P 2-J2=P 1 T Y P IC A L 1 8 5 17 20 23 70 25 200 22 500 11 -aS«JUUL/

1230A1

Contextual Info: 16 Megabit FLASH EEPROM D E N S E - P A C M I C K OS V S T M S \í DP5Z1MM16PY/I3/H3/J3/DP5Z1MW16PA3 AD VAN CED IN FO RM ATIO N DESCRIPTION: The DP5Z1MM16PY/Í3/H3/J3/DP5Z1MW16PA3 "SLCC" devices are a revolutionary new memory subsystem using Dense-Pac Microsystems'

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

Contextual Info: 41 DE M Dual NAND Gate, Schmitt Trigger E E E E E The 41 DE(M) device is a bipolar, NPN, sealed junction, silicon integrated circuit. It is available in a 16-pin plastic DIP. E D |T j3 3 j3 3 GND [ V Electrical Characteristics Vcc - 5.0 ±0.5 V, Tj = 0 to 85 ° C

30A18

Contextual Info: 8 Megabit FLASH EEPROM D EN SE-PA C DP5Z1MM8NKY/Í3/H3/J3/DP5Z1MX8NKA3 M I C K OS V S T \í M S PRELIM INARY D E SC R IP T IO N : The D P5Z1MM8NKY/Í3/H3/J3/DP5Z1MX8NKA3 "S L C C " devices are a revolutionary new memory subsystem using Dense-Pac Microsystems'

Contextual Info: F E AT U R E S MODEL NO. DSW261 82 0.5 - 30 MHz High Intercept Points 0.6 dB Insertion Loss 6 mA, ±15 VDC Non-Reflective TTL Control SP2T .10 .10 Ga As SP 2 T PART IDENTIFICATION .800 .25 J1 J1 J3 1.50±.03 J2 +15V E1 GND -15V 1.300 1.00±.03 J3 J2 .15±.05

40228

Contextual Info: lOOOpFj £ K V ELECTRICAL SPECIFICATIONS: NOTES 1.0 TURNS RATIO: P 6 - P 5 - P 4 : (J 6 -J3 ) ( P 3 - P 2 - P 1 ) : (J 2 -J1 ) 1CT : 1CT± 3% 1CT : 1CT ± 3% 2.0 INDUCTANCE : 350uH MIN. 0.1V, 350uH MIN. @ 0.1V, 3.0 LEAKAGE INDUCTANCE: 4.0 INTERWINDING CAPACITANCE : (P6.P5.P4) TO (J6.J3)

100C1032

Abstract: BNC T connectors INSERTION LOSS 100C10
Contextual Info: F E AT U R E S MODEL NO. 100C10 3 2 1 0 0 - 14 0 0 MHz 0.5 dB Insertion Loss 20 Watts CW TTL Driver SMA, BNC or TNC Connectors SP2T Medium Power PIN Diode SP2T 1.00±.03 2.75±.03 PART IDENTIFICATION 2.250 . 25 .50 J1 J3 J2 1.75 .06 . 25 J3 +5V CONT 1.250

TTL 4000

Contextual Info: F E AT U R E S .10 .10 .800 .25 K C TO Ga As SP 2 T S SP2T ED MODEL NO. CDS08 8 2 5 - 4 0 00 MHz 4 nSec Transition Time 27 nSec Switching Speed TTL Driver Non-Reflective Replaceable SMA Connectors J3 PART IDENTIFICATION J3 1.300 1.00±.03 J1 +5V CONT GND GND

Contextual Info: F E AT U R E S MODEL NO. DSW261 89 0.1 - 150 MHz High Intercept Points 2.5 mA, +15 VDC 60 dB Isolation SP2T .10 .10 Ga As SP 2 T PART IDENTIFICATION .800 .25 J1 J1 1.300 1.00±.03 J3 1.50±.03 +15V CONT GND -15V J2 • • J3 .15±.05 .106 DIA THRU 4 PLACES

Contextual Info: SHIELD 1000pF 2KV J8 J7 J6 J5 J4 J3 J2 J1 TR P4TRP4+ TR P2 TRP3TRP3 + TRP2 + TRP1 TR P1+ ELECTRICAL SPECIFICATIONS: 1.0 TURNS RATIO: P 3 - P 2 (P5-P4) (P9-P8) ( P 1 0 —P 1 1 ) 2.0 INDUCTANCE: (J4-J5) (J6-J3) (J8-J7) : (J2 —J ' 1 1 1 1 (P3-P2) ; (P5-P4)

Contextual Info: LOWER ROW D (D © ELECTRICAL SPECIFICATIONS: OPERATING TEMPERATURE RANGE: 1.0 TURNS RATIO: ( P 1 - P 2 - P 3 : ( J 1 - J 2 ) (P 4 -P 5 -P 6 ) : (J3 -J6 ) 2.0 INDUCTANCE: (P 6 -P 4 ) ( P 3 -P 1 ) 3.0 LEAKAGE INDUCTANCE: 4.0 INTERWINDING CAPACITANCE: (P 6.P5.P 4) TO (J6 .J3 )

ZR7BL05G

Abstract: EVAL-ADuC814QS R5232 p491 OP491 FM25640 r15j
Contextual Info: non Pow e r S u p p ly Re g u la tio n J3 and J4 O r ie n t a t i o n 9V E m u la t io n C on n e ctor non + 9V pop. ‘ J3 r j RXD J 3 -2 h TXD J 3 -3 h GND J 3 -4 I- J3 -5 h ZR7BL05G U1 ^|D 2 3 J2 -3 O - - f c j D 3 _ J 2 -2 o - IN R E V IS IO N R E C O R D

0725l

Contextual Info: lO O O p F j £ K V ELECTRICAL SPECIFICATIONS: NOTES 1.0 TURNS RATIO: P 6 - P 5 - P 4 : (J 6 -J3 ) ( P 3 - P 2 - P 1 ) : (J 2 -J1 ) 1CT : 1CT± 3% 1CT : 1CT ± 3% 2.0 INDUCTANCE : 350uH MIN. 0.1V, 350uH MIN. @ 0.1V, 3.0 LEAKAGE INDUCTANCE: 4.0 INTERWINDING CAPACITANCE : (P6.P5.P4) TO (J6.J3)

LTM8026EV

Abstract: walker
Contextual Info: 5 4 3 2 1 REVISION HISTORY COMP E1 D CTL_T E2 ECO REV - 2 DESCRIPTION PRODUCTION APPROVED DATE WALKER B. 10/?/11 CTL_I E3 D R1 10k R2 C1 100k E4 R3 R4 100k 301k 1% VOUT J3 VOUT 3.3V / 5A + J2 C CIN1 10uF 50V 1210 CIN2 22uF 50V GND J1 J2 J3 K1 K2 K3 L1 L2

Contextual Info: 5 4 3 2 ECO REV 1 COMP E1 D CTL_T E2 1 REVISION HISTORY DESCRIPTION APPROVED PRODUCTION DATE WALKER B. July 12, 2012 CTL_I E3 D R1 10k R2 C1 100k E4 R3 R4 100k 301k 1% VOUT J3 VOUT + J2 C CIN1 10µF 50V 1210 CIN2 22µF 50V GND J1 J2 J3 K1 K2 K3 L1 L2 L3 E7