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    JEDEC PACKAGE STANDARDS Search Results

    JEDEC PACKAGE STANDARDS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TPH9R00CQH Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation
    TPH2R408QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 120 A, 0.00243 Ohm@10V, SOP Advance Visit Toshiba Electronic Devices & Storage Corporation
    XPH2R106NC Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 110 A, 0.0021 Ω@10V, SOP Advance(WF) Visit Toshiba Electronic Devices & Storage Corporation
    XPH3R206NC Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 70 A, 0.0032 Ω@10V, SOP Advance(WF) Visit Toshiba Electronic Devices & Storage Corporation
    TPH4R008QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 86 A, 0.004 Ohm@10V, SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation

    JEDEC PACKAGE STANDARDS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    JEDEC Jc-11 free

    Abstract: Pub-95 TRANSISTOR Outlines JC11 JEP95 JEDEC diode Outlines IEC47D BGA OUTLINE DRAWING JEDEC bga case outline diode outlines
    Text: JEDEC Publication 95 Microelectronic Package Standard Application Report 1999 Printed in U.S.A. 0199 SZZA006 JEDEC Publication 95 Microelectronic Package Standard SZZA006 January 1999 1 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products


    Original     		PDF SZZA006 5M-1994, JEDEC Jc-11 free Pub-95 TRANSISTOR Outlines JC11 JEP95 JEDEC diode Outlines IEC47D BGA OUTLINE DRAWING JEDEC bga case outline diode outlines

    do-204ac footprint

    Abstract: DO-204AC F126 TP30-100 TP30-62 TP30-68 VDE0433 VDE0878
    Text: TP30-xxx Series  TRISILTM FEATURES BIDIRECTIONAL CROWBAR PROTECTION. VOLTAGE RANGE: FROM 62 V TO 270 V. HOLDING CURRENT : IH = 150 mA min. REPETITIVE PEAK PULSE CURRENT : IPP = 30 A, 10/1000 µs. JEDEC REGISTERED PACKAGE OUTLINE F126 JEDEC DO-204AC DESCRIPTION


    Original     		PDF TP30-xxx DO-204AC) ITU-K20 ITU-K17 VDE0433 VDE0878 do-204ac footprint DO-204AC F126 TP30-100 TP30-62 TP30-68 VDE0433 VDE0878

    SMP30-100

    Abstract: SMP30-120 SMP30-62 SMP30-68 VDE0433 VDE0878
    Text: SMP30-xxx Series  TRISILTM FEATURES BIDIRECTIONAL CROWBAR PROTECTION. VOLTAGE RANGE: FROM 62 V TO 270 V. HOLDING CURRENT : IH = 150 mA min. REPETITIVE PEAK PULSE CURRENT : IPP = 30 A, 10/1000 µs. JEDEC REGISTERED PACKAGE OUTLINE SMA JEDEC DO-214AA DESCRIPTION


    Original     		PDF SMP30-xxx DO-214AA) ITU-K20 ITU-K17 VDE0433 VDE0878 SMP30-100 SMP30-120 SMP30-62 SMP30-68 VDE0433 VDE0878

    SMP30-100

    Abstract: SMP30-120 SMP30-62 SMP30-68 VDE0433 VDE0878 TR-NWT001089
    Text: SMP30-xxx Series  TRISILTM FEATURES n n n n n BIDIRECTIONAL CROWBAR PROTECTION. VOLTAGE RANGE: FROM 62 V TO 270 V. HOLDING CURRENT : IH = 150 mA min. REPETITIVE PEAK PULSE CURRENT : IPP = 30 A, 10/1000 µs. JEDEC REGISTERED PACKAGE OUTLINE SMA JEDEC DO-214AA


    Original     		PDF SMP30-xxx DO-214AA) ITU-K20 ITU-K17 VDE0433 SMP30-100 SMP30-120 SMP30-62 SMP30-68 VDE0433 VDE0878 TR-NWT001089

    EP4CE15

    Abstract: MS 034 BGA and QFP Altera Package mounting Altera pdip top mark jedec package MO-247 SOIC 20 pin package datasheet QFN "100 pin" PACKAGE thermal resistance Theta JC of FBGA QFN148 EP4CE22
    Text: Altera Device Package Information Datasheet DS-PKG-16.2 This datasheet provides package and thermal resistance information for Altera devices. Package information includes the ordering code reference, package acronym, leadframe material, lead finish plating , JEDEC outline reference, lead


    Original     		PDF DS-PKG-16 EP4CE15 MS 034 BGA and QFP Altera Package mounting Altera pdip top mark jedec package MO-247 SOIC 20 pin package datasheet QFN "100 pin" PACKAGE thermal resistance Theta JC of FBGA QFN148 EP4CE22

    EP4CE6 package

    Abstract: EP4CE40 Altera EP4CE6 EP4CE55 5M240Z 5M1270Z QFN148 5m570z 5M40 5M80
    Text: Package Information Datasheet for Altera Devices DS-PKG-16.3 This datasheet provides package and thermal resistance information for Altera devices. Package information includes the ordering code reference, package acronym, leadframe material, lead finish plating , JEDEC outline reference, lead


    Original     		PDF DS-PKG-16 EP4CE6 package EP4CE40 Altera EP4CE6 EP4CE55 5M240Z 5M1270Z QFN148 5m570z 5M40 5M80

    BUV 481

    Abstract: bbg "marking" diode IPC7531 bbg marking st transil marking bbz ST BUN marking BBW smbj12a SMBJ24a SMBJ12A-TR
    Text: SMBJ Transil Features • Peak pulse power: – 600 W 10/1000 s ■ Stand off voltage range: from 5 V to 188 V ■ Unidirectional and bidirectional types ■ Operating Tj max: 150 °C ■ JEDEC registered package outline A K Unidirectional SMB (JEDEC DO-214AA)


    Original     		PDF DO-214AA) IEC61000-4-2 IEC61000-4-5 UL94V-0 MIL-STD-750, RS-481 IEC60286-3 IPC7531 BUV 481 bbg "marking" diode bbg marking st transil marking bbz ST BUN marking BBW smbj12a SMBJ24a SMBJ12A-TR

    smd transistor M7A

    Abstract: ED-7304-1 smd m7a uPD4011BG ED730 EIA and EIAJ tape standards ED-7417 EIA and EIAJ standards ED-7409 IEC-Publication-747
    Text: CONTENTS 1. STANDARDIZATION OF PACKAGES 1.1 EIAJ Standards 1.2 JEDEC Standards 1.3 IEC Standards 2. NAME'S OF NEC'S PACKAGES 3. PACKAGE CODES BY EIAJ 3.1 Construction of package code 4. DIMENSION SYMBOL AND EXAMPLE DIMENSIONS 4.1 Example of dimensions of packages


    Original     		PDF PD41265L-12-E1 PD41256L PD23C32000AGX-$ PD23C32000A smd transistor M7A ED-7304-1 smd m7a uPD4011BG ED730 EIA and EIAJ tape standards ED-7417 EIA and EIAJ standards ED-7409 IEC-Publication-747

    ST FBJ

    Abstract: SMCJ24A st fus diode IEC60286-3 SMCJ15CA SMCJ40A data sheet marking gbn STMicroelectronics MARKING CODE FUB 1SMCJ SMCJ48A
    Text: SMCJ Transil Features • Peak pulse power: – 1500 W 10/1000 s ■ Stand off voltage range: from 5 V to 188 V ■ Unidirectional and bidirectional types ■ Operating Tj max: 150 °C K ■ JEDEC registered package outline Unidirectional A SMC (JEDEC DO-214AB)


    Original     		PDF DO-214AB) IEC61000-4-2 IEC61000-4-5 UL94V-0 MIL-STD-750, RS-481 IEC60286-3 IPC7531 ST FBJ SMCJ24A st fus diode SMCJ15CA SMCJ40A data sheet marking gbn STMicroelectronics MARKING CODE FUB 1SMCJ SMCJ48A

    4146

    Abstract: No abstract text available
    Text: SMLVT3V3 Low voltage Transil Features • Peak pulse power 600 W 10/1000 s ■ Stand off voltage 3.3 V ■ Unidirectional type ■ Low clamping factor ■ Fast response time ■ JEDEC registered package outline A K SMB (JEDEC DO-214AA) Description The SMLVT3V3 is a Transil diode designed


    Original     		PDF DO-214AA) 4146

    Untitled

    Abstract: No abstract text available
    Text: SMLVT3V3 Low voltage Transil Features • Peak pulse power 600 W 10/1000 s ■ Stand off voltage 3.3 V ■ Unidirectional type ■ Low clamping factor ■ Fast response time ■ JEDEC registered package outline A K SMB (JEDEC DO-214AA) Description The SMLVT3V3 is a Transil diode designed


    Original     		PDF DO-214AA)

    JEDEC DO-214AA

    Abstract: marking sm DO-214AA DO-214AA 3v3 do-214aa footprint JESD97 DO-214AA diode SMLVT3V3
    Text: SMLVT3V3 Low voltage Transil Features • Peak pulse power 600 W 10/1000 s ■ Stand off voltage 3.3 V ■ Unidirectional type ■ Low clamping factor ■ Fast response time ■ JEDEC registered package outline A K SMB (JEDEC DO-214AA) Description The SMLVT3V3 is a Transil diode designed


    Original     		PDF DO-214AA) JESD97. Aug-2001 25-Apr-2007 JEDEC DO-214AA marking sm DO-214AA DO-214AA 3v3 do-214aa footprint JESD97 DO-214AA diode SMLVT3V3

    marking sm DO-214AA

    Abstract: SMLVT3V3 TM DO-214AA JESD97
    Text: SMLVT3V3 Low voltage Transil Features • Peak pulse power 600 W 10/1000 s ■ Stand off voltage 3.3 V ■ Unidirectional type ■ Low clamping factor ■ Fast response time ■ JEDEC registered package outline A K SMB (JEDEC DO-214AA) Description The SMLVT3V3 is a Transil diode designed


    Original     		PDF DO-214AA) marking sm DO-214AA SMLVT3V3 TM DO-214AA JESD97

    TE1204

    Abstract: ta7291 SSOP10 Package EIA481A RC-1009B
    Text: [ 4 ] Embossed Tape Specifications for Flat-Package Bipolar ICs [ 4 ] Embossed Tape Specifications for Flat-Package Bipolar ICs 1. Scope Specifications for embossed-tape packing for flat-package bipolar ICs and related issues such as ordering are usually in accordance with the relevant JEITA and JEDEC standards (RC-1009B and


    Original     		PDF RC-1009B EIA481A TE1204 TE1208 TA7291F TA7291F ta7291 SSOP10 Package

    schematic impulse sealer

    Abstract: XC4010E-PQ208 JEDEC Package Code MS-026-AED XC4013E-PQ240 JEDEC MS-026 footprint MS-026-ACB footprint jedec MS-026 TQFP 128 XC4013E-BG225 PG299-XC4025E bav 21 diode
    Text: Packages and Thermal Characteristics R February 2, 1999 Version 2.1 11* Package Information Inches vs. Millimeters The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in inches. The lead spacing is specified as 25, 50, or 100 mils (0.025", 0.050" or


    Original     		PDF

    footprint jedec MS-026 TQFP

    Abstract: JEDEC MS-026 footprint qfp 64 0.5 mm pitch land pattern fine BGA thermal profile schematic impulse sealer HQ208 PQ100 land pattern QFP 208 PQ208 TQ100
    Text: Packages and Thermal Characteristics R February 2, 1999 Version 2.1 11* Package Information Inches vs. Millimeters The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in inches. The lead spacing is specified as 25, 50, or 100 mils (0.025", 0.050" or


    Original     		PDF

    schematic impulse sealer

    Abstract: leadframe C7025 MO-151-BAR PG223-XC4013E XC4010E-PQ208 BGA 31 x 31 mm footprint jedec MS-026 TQFP 128 footprint jedec mo-067 XC4013E-PQ240 EIA standards 481
    Text: Packages and Thermal Characteristics R February 15, 2000 Version 2.1 8* Package Information Inches vs. Millimeters The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in inches. The lead spacing is specified as 25, 50, or 100 mils (0.025", 0.050" or


    Original     		PDF FG860 FG900 FG1156 schematic impulse sealer leadframe C7025 MO-151-BAR PG223-XC4013E XC4010E-PQ208 BGA 31 x 31 mm footprint jedec MS-026 TQFP 128 footprint jedec mo-067 XC4013E-PQ240 EIA standards 481

    TiO2

    Abstract: AA0177 PB10 PB12
    Text: SECTION 3 PACKAGING PACKAGE AND PIN-OUT INFORMATION This section contains package and pin-out information for the 100-pin Thin Quad Flat Pack TQFP configuration of the DSP56L811. All devices manufactured by Motorola conform to current JEDEC standards. Complete mechanical information regarding DSP56L811 packaging is available


    Original     		PDF 100-pin DSP56L811. DSP56L811 TiO2 AA0177 PB10 PB12

    schematic impulse sealer

    Abstract: qfp 64 0.4 mm pitch land pattern Rotron pk100 power supply XC4013E-PQ240 EFTEC-64 XC4010E-PQ208 MO-151-AAN-1 PK100 land pattern for TSOP 2 86 PIN
    Text: Packages and Thermal Characteristics: High-Reliability Products R 0 5 PK100 v1.0 June 15, 2000 Package Information Inches vs. Millimeters The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in inches. The lead spacing is specified as 25, 50, or 100 mils (0.025", 0.050" or 0.100").


    Original     		PDF PK100 060ROM schematic impulse sealer qfp 64 0.4 mm pitch land pattern Rotron pk100 power supply XC4013E-PQ240 EFTEC-64 XC4010E-PQ208 MO-151-AAN-1 PK100 land pattern for TSOP 2 86 PIN

    56QN50T18080

    Abstract: Senju MO-220-compliant Theta JA of 64-pin BGA 56RGQ senju solder paste MO-220 SN74SSTV16859 IPC-9701 qfn jc jb
    Text: Application Report SCEA032 - March 2003 56-Pin Quad Flatpack No-Lead Logic Package Frank Mortan and Lance Wright SLL Package Development ABSTRACT Texas Instruments TI Quad Flatpack No-Lead (QFN) 56-terminal package complies with JEDEC standard MO-220, allows for board miniaturization, and holds several advantages


    Original     		PDF SCEA032 56-Pin 56-terminal MO-220, 56QN50T18080 Senju MO-220-compliant Theta JA of 64-pin BGA 56RGQ senju solder paste MO-220 SN74SSTV16859 IPC-9701 qfn jc jb

    jesd 51-7

    Abstract: 63 ball Vfbga thermal resistance 56DL metcal apr 5000 MO-205 56ZQL BGA Ball Crack 054UG08C127 APR-5000
    Text: Application Report SZZA040 - December 2003 54BGA Package Frank Mortan SLL Package Development ABSTRACT The TI 54-ball low-profile, fine-pitch, ball grid array TFBGA meets dimensions specified in JEDEC MO-205, Variation DD. This 0.8-mm-pitch BGA allows economical OEM designs


    Original     		PDF SZZA040 54BGA 54-ball MO-205, 16-bit jesd 51-7 63 ball Vfbga thermal resistance 56DL metcal apr 5000 MO-205 56ZQL BGA Ball Crack 054UG08C127 APR-5000

    Untitled

    Abstract: No abstract text available
    Text: OM1905STM OM1912STM OM1915STM QM1905NTM OM1912NTM OM1915NTM ISOLATED HERMETIC FIXED VOLTAGE NEGATIVE REGULATORS APPROVED TO DESC DRAWINGS Three Terminal, Fixed Voltage, 1.5 Amp Precision Negative Regulators In Hermetic JEDEC TO-257AA Package FEATURES Isolated Hermetic Package, JEDEC TO-257AA Outline


    OCR Scan     		PDF OM1905STM OM1912STM OM1915STM QM1905NTM OM1912NTM OM1915NTM O-257AA T0-220

    HC2700JL

    Abstract: No abstract text available
    Text: HC2700LCC SERIES MyComp, Inc. +10 V, -10 V, and ±10 V Precision Vbltage References in JEDEC-Compatible Leadless Chip Carrier Packages FEATURES • 2700 - Type Reference in JEDEC-Compatible 28-Pin LCC Package • Standard Outputs of +10 V, -1 0 V, ±10 V • Kelvin Sense/Force


    OCR Scan     		PDF HC2700LCC 28-Pin HC2700LCC MIL-M-38510 MIL-STD-883 MILSTD-883 HC2700JL

    1500IC

    Abstract: No abstract text available
    Text: 6. Embossed Taping Specifications for Flat Packages 1. Scope Embossed taping package specification for bipolar IC flat package products and related matters are, as a rule, in accordance with EIAJ RC-1009B and JEDEC (EIA481A). 2. Shapes and Sizes of Tapes


    OCR Scan     		PDF EIA481A) RC-1009B) TE1204 TE1604, TE2412, 2mm/10-pitch. 106Q/cm. 1500IC