LMU217KMB55 Search Results

Contextual Info: L M U 1 7 / 2 1 7 16 x 16-bit Parallel multiplier FEATURES DESCRIPTION □ 45 ns W orst-C ase M u ltiply T im e □ Low P ow er C M O S T echnology □ R eplaces C ypress C Y 7C 517, ID T 7217L, and A M D A m 29517 □ Sin gle C lock A rchitectu re w ith R egister Enables

CERAMIC CHIP CARRIER LCC 68 socket

Abstract: LMU17DC LMU17 217g CY7C517 LMU17GC45 LMU17DM55 7217L
Contextual Info: LMU17/217 16 x 16-bit Parallel multiplier FEATURES DESCRIPTION □ 45 ns Worst-Case Multiply Time □ Low Power CMOS Technology □ Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 The LMU17 and LMU217 are high­ speed, low power 16-bit parallel multipliers. The LMU17 and LMU217

Contextual Info: LMU217 16 x 16-bit Parallel multiplier DEVICES INCORPORATED FEATURES □ 20 ns Worst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 □ Single Clock Architecture w ith Register Enables □ Two's Complement, Unsigned, or

Contextual Info: LMU217 16 x 16-bit Parallel multiplier DEV IC ES IN C O R PO R A TE D FEATURES □ 20 ns W orst-Case M ultiply Time □ Low P ow er CMOS Technology □ Replaces Cypress CY7C517, IDT 7217L, an d AMD Am29517 □ Single Clock A rchitecture w ith Register Enables

Contextual Info: LMU217 16 x 16-bit Parallel multiplier D E V IC ES IN C O R P O R A T E D FEATURES DESCRIPTION □ 4 5 n s W o rs t-C a s e M u ltip ly T im e □ L o w P o w e r C M O S T e c h n o lo g y □ R e p la c e s C y p re s s C Y 7 C 5 1 7 , ID T 7 2 1 7 L , a n d A M D A m 2 9 5 1 7

LMU217KMB55

Contextual Info: .»i> JLMU21Z m LMU217 16 x 16-bit Parallel multiplier DEVICES INCORPORATED FEATURES_ □ 20 ns Worst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Cypress CY7C517, IDT 7217L, and AM D Am29517 □ Single Clock Architecture with

5962-8768606TA

Abstract: LMU17GMB40 pwl 4700 II 5962-8768601ZX smd marking 12W 55GB
Contextual Info: REVISIONS LTR DATE DESCRIPTION APPROVED Y R -M O -D A A Changes in accordance w i t h N O R 5962-R106-94 94-01-20 M. L. PoeIking B Changes in accor d a n c e w i t h N O R 5 962-R044-95 94-12-27 M. L . P o elking C A d d device types 04, boilerplate. 97-04-17

Contextual Info: LMU217 16 x 16-bit Parallel m u ltip lie r DESCRIPTION FEATURES The LMU217 is a high-speed, low pow er 16-bit parallel multiplier. Full m ilitary ambient tem perature range operation is attained by the use of advanced CMOS technology. □ 20 ns W orst-C ase M ultiply Time

LMU217JC45

Abstract: LMU217JC35 CY7C517 LMU217 LMU217JC55 LMU217JC65
Contextual Info: LMU217 LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier 16 x 16-bit Parallel multiplier DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 20 ns Worst-Case Multiply Time ❑ Low Power CMOS Technology ❑ Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517

U17GM

Abstract: LMU217JC45 LMU17GC45 LMU17PC45 LMU17 amd k10 ma 8630 LMU17PC65 b1255 c0245
Contextual Info: LM U 17/217 1 6 x 1 6-bit Parallel Multiplier Features Description □ 45 ns worst-case multiply time The LMU17 and LMU217 are 16-bit parallel multipliers with high speed and low power consumption. They are pin and functionally compatible with AMD Am29517 devices. The

Contextual Info: LMU217 — — — L □ Low Power CMOS Technology □ Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 □ Single Clock Architecture with Register Enables □ Tw o’s Complement, Unsigned, or Mixed Operands □ Three-State Outputs □ DECC SMD No. 5962-87686