LOCK Search Results

Contextual Info: THIS DRAWING IS UNPUBLISHED. COPYRIGHT 2003 RELEASED FOR PUBLICATION APR ,2 0 0 3 . LOC ALL RIGHTS RESERVED. BY TYCO ELECTRONICS CORPORATION. E DIST R E V IS IO N S B LTR NOTES: C MATERIAL HOUSING : CONTACTS : SHELL : SCREW : BOARD LOCK : SCREW OF TORQUE THERMOPLASTIC, U L94V-0, BLACK

pbt-GF15

Abstract: AMP PBT-GF15 TYCO PBT-GF20 junior power timer pbtgf15 TYCO PBT-GF15
Contextual Info: 8 RELEASED FOR PUBLICATION FREI FUER VER0EFFENTLICHUN6 ,1968. lup INCORPORATED, rwrnppnpitfd ALL RIGHTS RESERVED. BY AHP alle REICHTE VORBEHALTEN. dv COPYRIGHT 1988 ï MATED WITH. IPASSEND ZU. ï ï ï LOC DI5T AI REVISIONS P PROJECT NR.i Pos 2 TO LOCK THE SEC. L O C K P U S H THE TWO

Contextual Info: BUCHANAN Catalog 1308389 Terminal locks Re vised 12-02 TW O-PIECE TERMINAL B LO C K CO NN EC TO RS Straight Header w/Locking Screw Flange, 5.0 mm Centerline, Color - Green Recommended PC Board Layout 5.00 UL Rating -300 V, 15 A No. of Positions Dim. A 2 5.0 [0.197]

UC2584

Contextual Info: UC1584 UC2584 UC3584 UNITRODE Secondary Side Synchronous Post Regulator FEATURES Practical Operation at Switching Frequencies up to 1MHz Wide Band Error Amplifier Undervoltage Lockout with Hysteresis Output Active Low During UVLO Soft Start/Maximum Duty Cycle

T 7411-1

Contextual Info: TYPES SN54111, SN74111 DUAL J-K MASTER-SLAVE FLIP-FLOPS WITH DATA LOCKOUT R E V IS E D DECEMBER 1983 S N 5 4 1 11 . . . J OR W PACKAGE • Package Options Include Plastic and Ceramic DIPs S N 7 4 1 11 . . . J OR N PACKAGE Dependable Texas Instruments Quality and

4-1634220-2

Contextual Info: THIS DRAWING IS UNPUBLISHED. COPYRIGHT 2003 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. APR ,2003- LOC ALL RIGHTS RESERVED. R E V IS IO N S DIST E B LTR c NOTES: 1. MATERIAL HOUSING : CONTACTS : SHELL : SCREW : BOARD LOCK : SCREW OE TORQUE 2. EINISH

frequency dividers

Abstract: Brushless Motors
Contextual Info: Motor Controls Phase Locked Controllers UC1633 Phase Locked Controller The UC1633 family of Phase Locked Controllers are com plete phase locked frequency control sys­ tems. While designed as precision speed control systems for DC motors, these devices are universal

Contextual Info: CD 9 8 .5 0 IO 1 5 .0 0 O r-. Tu CIRCUIT WP WP O- GROUND 0— O D GROUND CD OWITHOUT CARD CARD INSERTED WRITE PROTECT : LOCK CARD INSERTED WRITE PROTECT LOCK PATTERN PROHIBITED AR TYCO LOGO & PART NUMBER & DATE CODE o cu _ o in "st- tj o q C L:— 0.58

Contextual Info: THIS DRAWING IS UNPUBLISHED. COPYRIGHT 2003 RELEASED FOR PUBLICATION APR ,2003- LOC ALL RIGHTS RESERVED. BY TYCO ELECTRONICS CORPORATION. E DIST R E V IS IO N S B LTR c NOTES: SHELL : SCREW : BOARD LOCK DATE EBDO—0 0 9 5 —04 DWN APVD JMS FWK 0 9JA N 04

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP LOCK DRIVER WITH 3-STATE OUTPUTS SCAS378-APRIL 1994 ' Low Output Skew for lock-Distribution and lock-Generation Applications DL PACKAGE TOP VIEW * Operates at 3.3-V Vcc u ’ Distributes One lock Input to Six Outputs ' One Select Input Configures Up to Three

Contextual Info: SN54HC623, SN74HC623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS149A - DECEMBER 1982 - REVISED JANUARY 1996 Lock Bus-Latch Capability True Logic High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options include Plastic Small-Outline DW and Ceramic Flat

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP LOCK DRIVER WITH 3-STATE OUTPUTS _SCAS337B- FEBRUARY 1 9 9 3 - REVISED NOVEMBER 1996 * f • • • • • • Low Output Skew for lock-Dlstrlbutlon and lock-Generation Applications Operates at 3.3-V Vqc Distributes One lock Input to IWelve

bi directional dc motor speed controller

Abstract: current sinking circuit providing 100ma output current
Contextual Info: y UC1637 UC2637 UC3637 UNITRODE Switched Mode Controller for DC Motor Drive D E S C R IP T IO N ±2.5V to ±20V Input Supply Range • ±5% Initial Oscillator Accuracy; ± 10% Over Temperature • Pulse-by-Pulse Current Limiting • Under-Voltage Lockout This monolithic device contains a sawtooth oscillator, error amplifier, and two

CDC2510A

Contextual Info: CDC2510A 3.3-V PHASE-LOCK LOOP LOCK DRIVER SCAS604A– APRIL 1998 – REVISED JUNE 1998 D D D D D D D D D D PW PACKAGE TOP VIEW Spread Spectrum lock Compatible 100 MHz Maximum Frequency Available in Plastic 24-Pin TSSOP Phase-Lock Loop lock Distribution for

Contextual Info: TPS5100 TRIPLE-CHANNEL PWM CONTROL CIRCUITS SLVS169 – JANUARY 2000 D D D D D D D D D D PW PACKAGE TOP VIEW Low Voltage Operation . . . 2.5 V to 7 V Low Power . . . 3. 5 mA (f = 500 kHz, Duty = 50%) Internal Undervoltage Lockout Protection Internal Short Circuit Protection

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP LOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for lock-Distribution and lock-Generation Applications Operates at 3.3-V VCC Distributes One lock Input to Twelve

scas640

Contextual Info: CDCVF2505 3.3-V LOCK PHASE-LOCK LOOP LOCK DRIVER SCAS640 – JULY 2000 D D D D D D D D D D D D Phase-Lock Loop lock Driver for Synchronous DRAM and General-Purpose Applications Spread Spectrum lock Compatible Operating Frequency: 24 MHz to 200 MHz Low Jitter Cycle-cycle : <|150 ps| Over the

1.4957

Abstract: video splitter circuit diagram
Contextual Info: TRF3750 www.ti.com SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 HIGH-PERFORMANCE INTEGER-N PLL FREQUENCY SYNTHESIZER D D Lock Detect Output Digital and Analog D Versatile Hardware and Software Power Down D Packaged in a 16-Pin TSSOP Thin Quad FlatPack and a 20-Pin 4 x 4 mm QFN Package

Contextual Info: Quality Semiconductor, I nc. QS5940 SuperSync PCI Controller PLL lock Driver PRELIMINARY FEATURES/BENEFITS DESCRIPTION • • • • • • • • • • • QS5940 is a high-performance, low skew, low jitter phase-locked loop PLL lock driver. Two banks of

max31826

Abstract: MAX31826MUA Microcontroller Cross-Reference Q05n 260NC
Contextual Info: 19-6264; Rev 0; 3/12 MAX31826 1-Wire Digital Temperature Sensor with 1Kb Lockable EEPROM General Description The MAX31826 digital thermometer provides 12-bit temperature measurements and communicates over a 1-WireM bus that by definition requires only one data line

vq80

Abstract: A40MX02 one time
Contextual Info: Revision 3 40MX and 42MX Automotive FPGA Families Features High Capacity Ease of Integration • Single-Chip Applications ASIC Alternative for Automotive • Up to 100% Resource Utilization and 100% Pin Locking • 3,000 to 54,000 System Gates • Deterministic, User-Controllable Timing

Phase Discriminators

Abstract: Phase locked loops MIL-E-5400
Contextual Info: Model 20756 Without Video Amplifier Applications_ • Instantaneous Phase and Amplitude  Phase Locked Loops  S Parameter Measurements  Digital Phase Monitors Features_         2.0 – 4.0 GHz Excellent Phase Accuracy

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP LOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS378D - APRIL 1994 - REVISED APRIL 1996 • Low-Output Skew for lock-Dlstrlbution and lock-Generation Applications • • • Operates at 3.3-V Vqc Distributes One lock Input to Six Outputs

I-042-087

Abstract: 1-164892-8 164892
Contextual Info: 2 4 T H IS D R A W IN G IS U N P U B L IS H E D . BY ^ C O C O P Y R IG H T Kl RELEASED E L E C T R O N IC S C O R P O R A T IO N . FO R ALL P U B L IC A T IO N R IG H T S R E V IS IO N S RESERVED. H CONSISTS OF : LOCKING POSTS WASHERS SPRINGWASHERS NUTS [I jI