LV 373A Search Results

hd29050 hsop

Abstract: HD29050 hd2904 HD29050 H-SOP20 HD63084 hd29050 20 pin hd75107 74XXX244 HD151005 HE98134
Contextual Info: PRODUCTS LINE-UP 製品ラインアップ 3-1 PRODUCTS LINE-UP 3Vシリーズ シリーズ 3-2 PRODUCTS LINE-UP LV-Aシリーズ シリーズ 3-3 PRODUCTS LINE-UP 標準ロジック公表値の比較 HC LV LV-A AHC VHC 電源電圧 Vcc Vcc=2.5V スペック

Contextual Info: Philips Semiconductors Concise Catalogue 1996 INTEGRATED CIRCUITS GENERAL PURPOSE LOGIC Low-voltage series FIVE NEW LOW-VOLTAGE LOGIC FAMILIES Philips has introduced four low-voltage CMOS logic families and one new low-voltage BiCMOS family to complement their existing range of logic ICs: LV-HCMOS, LVC/LVC-A/LVC16, HLL, ALVC and LVT/LVT16. All five families are

Contextual Info: HD74LVG373A-Octal D-type Transparent Latches with 3-state Outputs Description The H D 7 4 LV C 3 7 3 A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical tS K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical t S K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical t S K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical tS K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

lvch16373a

Contextual Info: IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high­ speed, low-power latch is ideal for tem porary storage of

LVC16245

Abstract: LVC245 lcx245 LVC14A LCX16245 LVC 125A SCAA001 constant time delay lv 86A lvc16244A
Contextual Info: LVC CHARACTERIZATION INFORMATION 1 LVC COMPARISON TO OTHER LOWĆVOLTAGE LOGIC FAMILIES 2 LVC AND 5ĆV TOLERANCE A 5ĆV TOLERANT LVC - RELEASED DEVICES B FREQUENTLY ASKED QUESTIONS C TI'S LOWĆVOLTAGE PORTFOLIO D ADVANCED PACKAGING E 3 LVC CHARACTERIZATION INFORMATION

LVC16245

Abstract: philips semiconductor data handbook LCX16245 lcx245 SN74ALVCH16245 SN74LV245 SCAA001 SN74LVC245 SN74LVC245A SN74LVCH245
Contextual Info: LVC CHARACTERIZATION INFORMATION 1 LVC COMPARISON TO OTHER LOWĆVOLTAGE LOGIC FAMILIES 2 LVC AND 5ĆV TOLERANCE A 5ĆV TOLERANT LVC - RELEASED DEVICES B FREQUENTLY ASKED QUESTIONS C TI'S LOWĆVOLTAGE PORTFOLIO D ADVANCED PACKAGING E LVC DESIGNER'S GUIDE SCBA010

DIODE 4d

Abstract: IDT74LVCH32373A LVCH32373A
Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: – –

IDT74LVCH32373A

Abstract: LVCH32373A DIODE 4d
Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVCH32373A 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: – – – – – – –

Contextual Info: IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high­ speed, low-power latch is ideal for tem porary storage of

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FE A T U R E S : - D E S C R IP TIO N : Typical tSK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

LV 373A

Contextual Info: Philips Semiconductors Preliminary Specification Octal D-type transparent latch with 5-volt 74LVC373A to le ran tjn gu ts/o u tgu ts^ sta t^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 4 L V C H 3 7 3 A FEATURES • • • • • • • 5-Volt tolerant Inputs/outputs,

2N914

Abstract: 307G marking YJ transistors
Contextual Info: MIL-S-19500/373A 10 August 1972 dUi'X.ROC.UU'iU M IL-S-19500/373 USAF 31 May 1967 MILITARY SPECIFICATION SEMICONDUCTOR DEVICE, TRANSISTOR. NPN. SILICON, SWITCHING TYPES 2N914 AND TX2N914 This specification Is approved for use by all D epart­ ments and Agencies of the Departm ent of Defense.

HD2919

Abstract: HD151232 74LV1G HD268T26 hd26501 hd29050 hsop HD74LS90 HD14514 hd2904 marking 393 sop 8 pin
Contextual Info: 2001.2 Hitachi Unilogic Four Stages Ultra-High-Speed HD74ALVC1G/2G Series A new model has been added to the Hitachi unilogic series. Features The IC operates at high speed of tpd = 3 ns, which guarantees ultra-high-speed operation with 24-mA drive capability. Additionally, it has an input

IDT74LVCH16373A

Abstract: LVCH16373A
Contextual Info: Integrated Device Technology, Inc. 3.3V CMOS 16-BIT TRANSPARENT LATCH WITH BUS HOLD AND 5 VOLT TOLERANT I/O IDT74LVCH16373A ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: – Typical tSK o (Output Skew) < 250ps – ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical tSK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

IDT74LVC373A

Abstract: LVC373A
Contextual Info: 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSO P, 0.635mm pitch QSOP, 0.65mm pitch T S S O P packages

Contextual Info: 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP,

military radar 20 pages documentation

Contextual Info: SN74LVC373AĆEP OCTAL TRANSPARENT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCAS737B − NOVEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D D Typical VOLP Output Ground Bounce − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: SN54LVC373A, SN74LVC373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS www.ti.com SCAS295S – JANUARY 1993 – REVISED MAY 2005 • 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE ABC 1Q 1D 2D 2Q 3Q 3D 4D 4Q 20 2

26c32a

Abstract: schematic thyristor based inverter LV1GW16A 151011 IC TSSOP-24 ASSP for Power Management Applications working of IC 4017 inverter t 151011 174 HC 4053A HC 4066A RJP4002ANS
Contextual Info: 2008.11 Renesas General-Purpose Logic ICs General Catalog www.renesas.com Full Lineup of General-Purpose Logic IC Matching with Advanced Needs The extended Renesas General Logic g lineup p fullyy covers customers' various needs. Indeed, our General-Purpose Logic technology has been tailor-made for the IT era by