LVCH573A Search Results

IDT74LVCH573A

Abstract: LVCH573A
Contextual Info: LVCH573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: LVCH573A ADVANCE INFORMATION signed specifically for driving highly capacitive or relatively low-impedance

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

573AD

Abstract: 74LVC573A 74LVCH573A LVCH573A
Contextual Info: Philips Semiconductors Preliminary Specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; 3-state FEATURES • • • • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic. Wide supply voltage range of 2.7 V to 3.6 V.

Contextual Info: Philips Semiconductors Preliminary Specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; 3-state FEATURES • • • • • • • • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic. Wide supply voltage range of

Contextual Info: LVCH573A ADVANCE INFORMATION 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS HOLD FEATURES: - tive or relatively low-impedance loads, and is particularly suit­ able for implementing buffer registers, input-output I/O ports,

Contextual Info: LVCH573A ADVANCE INFORMATION 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS HOLD FEATURES: - tive or relatively low-impedance loads, and is particularly suit­ able for implementing buffer registers, input-output I/O ports,

IDT74LVCH573A

Abstract: LVCH573A
Contextual Info: LVCH573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: LVCH573A signed specifically for driving highly capacitive or relatively low-impedance

IDT74LVCH573A

Abstract: LVCH573A 3.3v to 5v buffer latch
Contextual Info: LVCH573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: LVCH573A DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

Contextual Info: 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FE A T U R E S : - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSO P,

74LVC573A

Abstract: 74LVC573AD 74LVC573ADB 74LVC573APW 74LVCH573A 74LVCH573AD 74LVCH573ADB 74LVCH573APW LVCH573A
Contextual Info: Product specification Philips Semiconductors Octal D-type transparent latch with 5-volt tolerant inputs/outputs; 3-State 74LVC573A LVCH573A Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of