LVDS LEVEL TRANSLATOR Search Results

IN50

Abstract: MAX9180 MAX9181 MAX9181EXT-T SC70-6
Contextual Info: 19-2415; Rev 0; 4/02 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9181 is an LVPECL-to-LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output. It is ideal for interfacing between

LVPECL multidrop

Abstract: IN50 MAX9180 MAX9181 MAX9181EXT-T SC70-6
Contextual Info: 19-2415; Rev 1; 2/04 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9181 is an LVPECL-to-LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output. It is ideal for interfacing between

Contextual Info: 19-2415; Rev 1; 2/04 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9181 is an LVPECL-to-LVDS level translator that accepts a single LVPECL input and translates it to a single LVDS output. It is ideal for interfacing between

VSC6431

Abstract: VSC6432 LVDS Level Translator 333Mhz
Contextual Info: 333Mb/s 17 Channel LVDS to ECL Level Translator VSC6431 Product Brief Timing and Logic Features: • 333MHz / 333Mb/s Operation • ECL to LVDS Level Translation • -2V and +3.3V Power Supplies • 128-pin Thermally Enhanced PQFP Packaging • 16 Data Channels, 1 Frame

Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

C101

Abstract: SN65CML100 SN65CML100D SN65CML100DGK TDS6604
Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

vid 200

Abstract: C101 SN65CML100 SN65CML100D SN65CML100DGK TDS6604
Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES DESCRIPTION D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives

Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES • • • • • • • • • • DESCRIPTION Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML Signaling Rates 1 up to 1.5 Gbps

C101

Abstract: SN65CML100 SN65CML100D SN65CML100DGK TDS6604
Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES • • • • • • • • • • DESCRIPTION Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML Signaling Rates 1 up to 1.5 Gbps

Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES • • • • • • • • • • DESCRIPTION Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML Signaling Rates 1 up to 1.5 Gbps

C101

Abstract: SN65CML100 SN65CML100D SN65CML100DGK TDS6604
Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES • • • • • • • • • • DESCRIPTION Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML Signaling Rates 1 up to 1.5 Gbps

C101

Abstract: SN65CML100 SN65CML100D SN65CML100DGK TDS6604 CML100
Contextual Info: SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES • • • • • • • • • • DESCRIPTION Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML Signaling Rates 1 up to 1.5 Gbps

N100

Abstract: NB100LVEP91 NB100LVEP91DW NB100LVEP91DWR2
Contextual Info: NB100LVEP91 2.5V / 3.3V Any Level Positive Input to −2.5V / −3.3V / −5V NECL Output Translator The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

N100

Abstract: NB100LVEP91
Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

MC100EP91

Abstract: MC100EP91DW MC100EP91DWG
Contextual Info: MC100EP91 2.5 V/3.3 V Any Level Positive Input to −3.3 V/−5.5 V NECL Output Translator http://onsemi.com Description The MC100EP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential NECL

20CML

Contextual Info: NB4L16M 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer/ Translator with Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL

Contextual Info: 19-2216; Rev 0; 10/01 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package The MAX9156 operates from a single +3.3V supply and consumes only 10mA supply current over a -40°C to +85°C temperature range. It is available in a tiny 6-pin

AN253

Abstract: AN-253 PTN3310 PTN3311 Signal Path Designer SW00680
Contextual Info: INTEGRATED CIRCUITS AN253 PTN3310 and PTN3311 LVDS-PECL translators bring significant benefits in high-speed networking and telecom applications Author: Kristina Avrionova Philips Semiconductors 2001 Jan 03 Philips Semiconductors Application note PTN3310 and PTN3311 LVDS-PECL translators bring significant

BBU RRU

Contextual Info: LMK00301 3-GHz, 10-Output Differential Fanout Buffer / Level Translator 1.0 General Description The LMK00301 is a 3-GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from

Contextual Info: LMK00304 3-GHz 4-Output Differential Clock Buffer/Level Translator 1.0 General Description • Servers, Workstations, and Computing The LMK00304 is a 3-GHz 4-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution