Untitled
Abstract: No abstract text available
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform 2 (UB & LB controlled)
|
Original
|
PDF
|
LY61L6416
48-ball
-20ns
44-pin
|
Untitled
Abstract: No abstract text available
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform 2 (UB & LB controlled) Revised the typo in Page 1
|
Original
|
PDF
|
LY61L6416
LY61L6416
576-bit
44-pin
|
Untitled
Abstract: No abstract text available
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.2 FEATURES GENERAL DESCRIPTION Fast access time : 8/10/12/15ns Low power consumption: Operating current : 115/105/95/85mA TYP. Standby current : 0.6mA (TYP.) Single 3.3V power supply All inputs and outputs TTL compatible
|
Original
|
PDF
|
LY61L6416
LY61L6416
576-bit
8/10/12/15ns
115/105/95/85mA
44-pin
|
LY61L6416
Abstract: TFBGA
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.9 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Rev. 1.8 Rev. 1.9 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform 2 (UB & LB controlled)
|
Original
|
PDF
|
LY61L6416
48-ball
-20ns
44-pin
LY61L6416
TFBGA
|
Untitled
Abstract: No abstract text available
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Rev. 1.8 Rev. 1.9 Rev. 2.0 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform 2 (UB & LB controlled)
|
Original
|
PDF
|
LY61L6416
48-ball
-20ns
|
Untitled
Abstract: No abstract text available
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.6 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform 2 (UB & LB controlled)
|
Original
|
PDF
|
LY61L6416
48-ball
-20ns
Y61L6416
44-pin
|
Untitled
Abstract: No abstract text available
Text: LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform 2 (UB & LB controlled) Revised the typo in Page 1
|
Original
|
PDF
|
LY61L6416
48-ball
LY61L6416
44-pin
|
CS16LV40963
Abstract: BS62LV4006 sram cross reference CS18LV40963 LY6264 Hynix Cross Reference cs18lv10245 cs18lv02560 LY621024 K6X1008C2D
Text: www.ashlea.co.uk 01793 783784 Low power SRAM Cross Reference Density Configuration 64K 8Kx8 256K 32Kx8 Lyontek LY6264 LY62L64 LY62256 LY62L256 LY62256 2.7-5.5 1M 128Kx8 64Kx16 LY621024 LY62L1024 LY62L6416 Samsung K6X0808C1D K6X0808T1D K6X1008C2D K6X1008T2D
|
Original
|
PDF
|
32Kx8
LY6264
LY62L64
LY62256
LY62L256
LY62256
128Kx8
64Kx16
LY621024
LY62L1024
CS16LV40963
BS62LV4006
sram cross reference
CS18LV40963
LY6264
Hynix Cross Reference
cs18lv10245
cs18lv02560
LY621024
K6X1008C2D
|
Untitled
Abstract: No abstract text available
Text: Page:1/1 Update: January 9, 2015 High Speed SRAM Density 64K Configuration 8K x 8 Power Supply 5V 5V 256K Item No. Speed ns LY6164 Isb 12/15 1.0mA(typ) LY61256 12/15 0.5mA(typ) Operating Temp. (*1) Data Sheet C/E/I C/E/I 32K × 8 3.3V LY61L256 12/15 0.5mA(typ)
|
Original
|
PDF
|
LY61L256
LY61L1288
LY611024
LY61L1024
LY61L2568
20LL/25LL
LY6112816
LY61L12816
|