M54HC11 Search Results

74hc112

Contextual Info: M54HC112 M74HC112 SCSTHOMSON m DUAL J-K FLIP FLOP WITH PRESET AND CLEAR a HIGH SPEED fMAX = 59 MHz Typ. at VCC= 5V LOW POWER DISSIPATION lCC = 2 (iA at Ta = 25°C • HIGH NOISE IMMUNITY VNIH = VNIL= 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

IC 74HC112

Abstract: H74HC112 74LS112 J-K flip flop clock inputs 54HC 74HC M54HC112 M74HC112 H11L 74ls112 pin diagram
Contextual Info: HS-CMOS" INTEGRATED CIRCUITS a M54HC112 M74W112 4 147 z /~ P R E L IM IN AmRVY Di DATA DUAL J-K FLIP FLOP W ITH PRESET AND CLEAR DESCRIPTION The M 5 4 /7 4 H C 1 12 is the high speed C M O S DUAL J-K FL IP -F L O P W IT H P R E S E T A N D C LE A R fabricated in silicon ga te C 2M O S technology. It

or gate thruth table

Contextual Info: M54HC113 M74HC113 Æ 7 SCS-THOM SON ^ 7 # R if lQ ^ Q i[ L [ l( g ir [S @ M D ( g i DUAL J-K FLIP FLOP WITH PRESET • HIGH SPEED fMAX= 64 MHz (Typ.) at V c c = 5 V LOW POWER DISSIPATION ICC = 2 at TA = 25° C ■ HIGH NOISE IMMUNITY VniH = V n il= 28% VCc (MIN.)

Contextual Info: _ 5 b E D • 7 ^ 5 3 7 O üam S OTG ■ S G T H _ / 3 T SGS-THOM SON M54HC11 ^T #n, BMOMilLli gTrMlD i_M74HC11 S G S-THOMSON TRIPLE 3-INPUT AND GATE ■ HIGH SPEED tpo = 10 ns (TYP. at V c c = 5V ■ LOW POW ER DISSIPATION

TF311

Abstract: JK flip flop IC JK flip flop IC diagram M54HC112 M54HC112D M54HC112K
Contextual Info: M54HC112 RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

74hc113

Abstract: or gate thruth table 54HC 74HC M54HC113 M74HC113
Contextual Info: Æ 7 SGS-THOMSON Ä 7# M54HC113 M74HC113 [ M lO g ^ [ i[ L [ l( g ,F [ ^ © l i O ( g S DUAL j - k f l ip f l o p w it h p r e s e t • HIGH SPEED fMAX= 64 MHz (Typ. at V q c = 5V LOW POWER DISSIPATION Ic e = 2 iiA at Ta = 2 5 °C i HIGH NOISE IM M U N ITY

74LS11 circuit diagram with voltage

Abstract: 74hc11
Contextual Info: M54HC11 M74HC11 SGS-THOMSON TRIPLE 3-INPUT AND GATE HIGH SPEED tPD = 10 ns TYP. at VCc = 5V LOW POWER DISSIPATION Ice = 1 (MAX.) at Ta = 25°C HIGH NOISE IMMUNITY = 28% V cc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS V N IH = V N IL SYMMETRICAL OUTPUT IMPEDANCE

74HC112 pin diagram

Abstract: 74ls112 function table 74HC112
Contextual Info: M54HC112 M74HC112 SGS-THOMSON G L ì[LI TF[^ 5 RQ0© i DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX= 59 MHz (Typ.) at VCC= 5V LOW POWER DISSIPATION Icc = 2 at TA = 25°C ■ HIGH NOISE IMMUNITY V nih = V Nil = 28% Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

54HC

Abstract: 74HC C113 M54HC113 M74HC113 74HC113
Contextual Info: H S-CM O S INTEGRATED ¿ \\° \ CIRCUITS M54HC113 M74HC113. 4 P R E L IM IN A R Y D A T A DUAL J-K FLIP FLOP WITH PRESET DESCRIPTION T h e M 5 4 /7 4 H C 1 13 is a hig h s p e e d C M O S D U A L J-K FLIP FLO P W ITH P R E S E T fa b ric a te d in silicon

Contextual Info: M54HC11 M74HC11 A 7# Rii]D g^(Q ILi Tr[E(Q)lR!]0©i Æ 7 S G S - T H O M S O N TRIPLE 3-INPUT AND GATE • HIGH SPEED tpo = 10 ns (TYP.) at V c c = 5V ■ LOW POWER DISSIPATION Ice = 1 /*A (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY V nih = V n il = 2 °/° ^CC (MIN.)

74hc113

Abstract: T flip flop IC Toggle flip flop IC "J-K Flip flop" LS113 M74HC113B1R M74HC113C1R M74HC113M1R M54HC113 M54HC113F1R
Contextual Info: M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET . . . . . . . . HIGH SPEED fMAX = 71 MHz TYP. at VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

54HC

Abstract: 74HC M54HC11 M74HC11 74HC 84 B1-M74HC11
Contextual Info: HS-CMOS M54HC11 M74HC11 INTEGRATED CIRCUITS o PRELIMINARY DATA TRIPLE 3-INPUT AND GATE D ES C R IPTIO N The M54/74HC11 is a high speed C M O S T R IP L E 3-INPUT AND G A T E fabricated in silicon gate C 2M O S technology. It has the same high speed performance of L S T T L combined with true C M O S

M54HC112

Abstract: M54HC112D M54HC112K
Contextual Info: M54HC112 RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

74HC112

Abstract: 74LS112 JK EDGE TRIGGERED FLIP FLOP
Contextual Info: f Z T SGS-THOMSON ^ 7 # « [fM L E O ïM K S M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . HIGHSPEED fMAX = 67 MHz TYP. AT Vcc = 5 V • LOW POWER DISSIPATION Ice = 2 |jA AT T a = 25 ’C ■ HIGH NOISE IMMUNITY V nih = V n il = 28 % V c c (MIN.)

M74HC11B1R

Abstract: M54HC11 M54HC11F1R M74HC11 M74HC11C1R M74HC11M1R 74ls11 ic
Contextual Info: M54HC11 M74HC11 TRIPLE 3-INPUT AND GATE . . . . . . . . HIGH SPEED tPD = 7 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

IC 74HC112

Abstract: JK flip flop IC diagram 74LS112 JK EDGE TRIGGERED FLIP FLOP 74ls112 pin diagram 74ls112 function table 74HC112 Toggle flip flop IC M54HC112 M54HC112F1R M74HC112
Contextual Info: M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

Contextual Info: SGS-THOMSON M54HC11 M74HC11 TRIPLE 3-INPUT AND GATE • HIGHSPEED tpD = 7 ns TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 1 |iA (MAX.) AT Ta = 25 "C ■ HIGH NOISE IMMUNITY Vnih = V n il = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTLLOADS ■ SYMMETRICAL OUTPUT IMPEDANCE

Contextual Info: r Z Z SGS-THOMSON Ä 7# M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET • HIGHSPEED fMAX = 71 MHz TYP. at VCC = 5 V ■ LOW POWER DISSIPATION Icc = 2 pA at Ta = 25 'C - HIGH NOISE IMMUNITY Vnih = V n il = 28 % V c c (MIN.) ■ OUTPUT DRIVE CAPABILITY

M54HC11

Abstract: M54HC11D M54HC11K M54HC11K1
Contextual Info: M54HC11 RAD-HARD TRIPLE 3-INPUT AND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 9ns TYP. at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

74HC112 pin diagram

Abstract: 74hc112 IC 74HC112 74ls112 waveform 74HC74 54HC 74HC M54HC112 M54HC112F1 M74HC112
Contextual Info: M54HC112 M74HC112 S G S -T H O M S O N K * [ f 3 HkHOT®üao S DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX= 59 MHz Typ. at V c c = 5V LOW POWER DISSIPATION Ic c = 2 /iA at TA = 25 °C ■ HIGH NOISE IM M U NITY V n IH = V n i l = 28°/ o VCC (MIN.)

940900701F

Abstract: 54HC4053 54HC273 940501301F 920305001F 940104801F 920110601F 54HC08 920112001F 940806401F
Contextual Info: M54HCxxx M54HCTxxx Rad-hard high speed 2 to 6 V CMOS logic series Features • 2 to 6 V operating voltage ■ Low power DC dissipation: 1 µA max at 25°C ■ High speed tPD = 8 ns typ at 25°C ■ Symmetrical outputs characteristics ■ High noise immunity: 28% of min VCC

M54HC132

Abstract: M54HC595KG M54HC138KG 920112001F
Contextual Info: M54HCxxx, M54HCTxxx Rad-hard high speed 2 to 6 V CMOS logic series Datasheet - production data Features • 2 to 6 V operating voltage • Low power DC dissipation: 1 µA max. at 25 °C • High speed tPD = 8 ns typ. at 25 °C • Symmetrical outputs characteristics

Contextual Info: _ Sb E D • 7*^237 GOSSflMb 6 3 1 ■ S G T H _ / S T S C S -m O M S O N ^ 7 # H D ^ L [ l © ™ K 3D©i S M 5 4 H C 1 13 M 7 4 H C 113 T -M -0 7 -O 7 DUAL J-K FLIP FLOP WITH PRESET G S-THOMSON ■ HIGH SPEED fMAX= 64 MHz Typ. at V c c = 5V

Contextual Info: SbE D • 7 * ^ 2 3 7 OGB'îflm 2S7 ■ S G T H S G S -T H O M S O N M 5 4 H C Ï 12 LiOT KDD i M 7 4 H C 1 12 6 S-THOMSON ’T-HÙ-ÔT-OT DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED fMAX = 59 MHz (Typ. at VCC= 5V LOW POWER DISSIPATION Ice = 2 jiA at TA = 25°C