M80C186XL Search Results

Contextual Info: i i r t r J Ä i M @ l O M IF C O M A Y O !* ] M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of M80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

SAL 41B

Abstract: 8088 instruction set CTX 12S RD smd lm 398- SAMPLE AND HOLD
Contextual Info: Ä in te i I M K l l O M I F iO M A T O ! * ! M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Low Power, Full Static Version of M80C186 ■ Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

Fortran-86

Abstract: intel 8088 memory 8088 instruction set intel 80186 memory map 80C186XL 80c187
Contextual Info: in te i Ä W Ä l O N IP Q IR G M irO lD N M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of M80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

80C186

Abstract: 80C187 M80C186 M80C186XL M80C186XL12 M80C186XL16 M80C186XL20
Contextual Info: M80C186XL20 16 12 10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Y Low Power Full Static Version of M80C186 Y Operation Modes Enhanced Mode DRAM Refresh Control Unit Power-Save Mode Direct Interface to 80C187 Compatible Mode NMOS 80186 Pin-for-Pin Replacement for Non-Numerics

Contextual Info: M80C186XL AC CHARACTERISTICS MAJOR CYCLE TIMINGS READ CYCLE Tc = —55°C to + 125°C, VCc = 5V ±10% All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C l = 50 pF. For AC tests, input V|_ = 0.45V and Vm = 2.4V except at X1 where V ih = V cc ~ 0.5V.

Contextual Info: M80C186XL DERATING CURVES Figure 18. CMOS Level Rise and Fait Times for Output Buffers ASWAN ! 3-93

Contextual Info: M80C186XL ABSOLUTE MAXIMUM RATINGS* Case Temperature under Bias . . - 55°C to + 125°C Storage Temperature .-6 5 °C to +150°C Voltage on Any Pin with Respect to Ground. - 1 ,0V to + 7.0V /Package Power Dissipation.1W

Contextual Info: M80C186XL M80C186XL EXECUTION TIMINGS A determination of M 80C186XL program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of exe­ cution unit cycles necessary to execute instructions. The following instruction timings represent the mini­

tcl 110011 ic

Abstract: lm 398- SAMPLE AND HOLD
Contextual Info: inte1 M W l M fT O B R M B T O N ] M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of M80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

m8087 intel

Contextual Info: p R iy iM O B y w in te i M80C187 80-BIT NUMERIC PROCESSOR EXTENSION Military High Perform ance 80-Bit Internal Architecture Tw o to Three Tim es M8087 Perform ance at Equivalent Clock Speed Im plements A N S I/IE E E Standard 7541985 fo r Binary Floating-Point

MG80C186-12

Abstract: MG80C186 MQ80C186-12 MG80C186-10 MG80C186XL12 MG80C186XL 5962-8850102ZA MG80C186-10/BZC MG80C18610 5962-8850101ZC
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Technical changes were made in table I, Editorial changes throughout. 90-08-15 William K. Heckman B Changes in accordance with NOR 5962-R023-92. 91-10-30 Monica L.Poelking C Changes in accordance with NOR 5962-R189-93.