M80C186 Search Results

Contextual Info: i i r t r J Ä i M @ l O M IF C O M A Y O !* ] M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of M80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

SAL 41B

Abstract: 8088 instruction set CTX 12S RD smd lm 398- SAMPLE AND HOLD
Contextual Info: Ä in te i I M K l l O M I F iO M A T O ! * ! M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Low Power, Full Static Version of M80C186 ■ Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

mg80c186

Abstract: 523ap order 231369 M801 80C186EB
Contextual Info: in te i M80C186EB-16, -13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Full Static Operation • True CMOS Inputs and Outputs • —55°C to + 125°C Operating Temperature Range • Integrated Feature Set — Low-Power Static CPU Core — Two Independent UARTs each with

M801

Abstract: M80C186
Contextual Info: M80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR M ilitary • Direct Addressing Capability to 1 Mbyte and 64 Kbyte I/O ■ Operation Modes Include: — Enhanced Mode Which Has — DRAM Refresh — Power-Save Logic — Direct Interface to New CMOS Numerics Coprocessor

Contextual Info: M80C186EB ERRATA REVISION HISTORY The current stepping B step of the M 80C186EB has the following known functional anomaly. The first revision of this data sheet (271214-001) in­ dicated only 8 MH z and 13 M H z availability. The M 80C 186EB will also be available in a 16 M H z ver­

Fortran-86

Abstract: intel 8088 memory 8088 instruction set intel 80186 memory map 80C186XL 80c187
Contextual Info: in te i Ä W Ä l O N IP Q IR G M irO lD N M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of M80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

001100dw

Contextual Info: M80C186EB INSTRUCTION SET SUMMARY Clock C yd— Format Comments DATA TRANSFER MOV = Move: Register to Register/Memory 1 0 0 Q1 QOw mod reg r/m 2/12 Register/memory to register 1000101w mod reg r/m 2/9 Immediate to register/memory 1 10001 1w mod 000 r/m data

ocs4

Contextual Info: M80C186EB PACKAGE INFORMATION This section describes the pins, pinouts, and thermal characteristics for the M80C186EB PGA package. For complete package specifications and informa­ tion, see the Intel Packaging Outlines and Dimen­ sions Guide Order Number: 231369 .

80C186

Abstract: 80C187 M80C186 M80C186XL M80C186XL12 M80C186XL16 M80C186XL20
Contextual Info: M80C186XL20 16 12 10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Y Low Power Full Static Version of M80C186 Y Operation Modes Enhanced Mode DRAM Refresh Control Unit Power-Save Mode Direct Interface to 80C187 Compatible Mode NMOS 80186 Pin-for-Pin Replacement for Non-Numerics

MG80C186

Abstract: TRANSISTOR IFW 82 MG80C 27121 MG80C186EB
Contextual Info: M SM AGM &E O M F@ ^R M Y O M in te i M80C186EB-16, -13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Full Static Operation • True CMOS Inputs and Outputs • - 55°C to + 125°C Operating Temperature Range Integrated Feature Set — Low-Power Static CPU Core

Contextual Info: M80C186EB BUS CYCLE WAVEFORMS Figures 19 through 25 present the various bus cy­ cles that are generated by the M80C186EB. What is shown in the figure is the relationship of the various bus signals to CLKOUT. These figures along with the information present in AC Specifications allow

M80C188

Abstract: UPPER10 GCS2
Contextual Info: M80C186EB INTRODUCTION The M80C186EB is the first product in a new gener­ ation of low-power, high-integration microproces­ sors. It enhances the existing 186 family by offering new features and new operating modes. The M80C186EB is object code compatible with the

MG80C186

Abstract: MG80C186EB M80C186 80C186EB
Contextual Info: intei M80C186EB-16,-13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Full Static Operation • True CMOS Inputs and Outputs • -55°C to + 125°C Operating Temperature Range • Integrated Feature Set — Low-Power Static CPU Core — Two Independent UARTs each with

Contextual Info: M80C186EB 88-LEAD CERAMIC PIN GRID ARRAY PACKAGE SEATINGPLANE A It il SEATING— H PLANE r=- e, 0 6 ALL PINS SWAGGED PIN DETAIL A,—* BASE — PLANE 271 214-33 Family: Ceramic Pin Grid Array Package Symbol Millimeters Inches Min Max Notes A 3.56 4.57 Ai

Contextual Info: M80C186EB RESET The M80C186EB will perform a reset operation any time the RESIN pin active. The RESIN pin Is actually synchronized before it is presented internally, which means that the clock must be operating before a reset can take effect. From a power-on state, RESIN

Contextual Info: M80C186XL AC CHARACTERISTICS MAJOR CYCLE TIMINGS READ CYCLE Tc = —55°C to + 125°C, VCc = 5V ±10% All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C l = 50 pF. For AC tests, input V|_ = 0.45V and Vm = 2.4V except at X1 where V ih = V cc ~ 0.5V.

Contextual Info: M80C186XL DERATING CURVES Figure 18. CMOS Level Rise and Fait Times for Output Buffers ASWAN ! 3-93

Contextual Info: M80C186EB AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 9. See the Derating Curves section to see how timings vary with load capacitance. Specifications are measured at the V cc/2 crossing point, unless otherwise specified. See AC Timing

Contextual Info: intei M80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR Military I Operation Modes Include: — Enhanced Mode Which Has — DRAM Refresh — Power-Save Logic — Direct Interface to New CMOS Numerics Coprocessor — Compatible Mode — NMOS M80186 Pin for Pin

Contextual Info: M80C186XL ABSOLUTE MAXIMUM RATINGS* Case Temperature under Bias . . - 55°C to + 125°C Storage Temperature .-6 5 °C to +150°C Voltage on Any Pin with Respect to Ground. - 1 ,0V to + 7.0V /Package Power Dissipation.1W

MG80C186

Abstract: MG80C186EB M80C188 m80c187 M80C186EB-13 order 231369 M80C186EB-16 M80C186EB-8 AD947 MG80C
Contextual Info: M80C186EB-16 -13 -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR  Full Static Operation  True CMOS Inputs and Outputs  b55 C to a 125 C Operating Temperature Range Integrated Feature Set Low-Power Static CPU Core Two Independent UARTs each with an Integral Baud Rate Generator

AD1501

Contextual Info: M80C186EB in t e l AC SPECIFICATIONS A C Characteristic»— M80C186EB-16 Symbol Parameter Min Max Units Notes Frequency Period High Time Low Time Rise Time Fall Time 31.25 10 10 1 1 32 oo oo oo 8 8 MHz ns ns ns ns ns 1 1 1,2 1,2 1,3, 11 1, 3,11 CLKIN to C LKO U T Delay

Contextual Info: M80C186XL M80C186XL EXECUTION TIMINGS A determination of M 80C186XL program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of exe­ cution unit cycles necessary to execute instructions. The following instruction timings represent the mini­

270500

Abstract: M80286 M80C186
Contextual Info: inU M80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR Military Direct Addressing Capability to 1 Mbyte and 64 Kbyte I/O Completely Object Code Compatible with All Existing M8086/M8088 Software and Also Has 10 Additional Instructions over M8086/M8088 Complete System Development