MAD43 Search Results

47d-15

Contextual Info: STP3020 S un M ic r o e l e c t r o n ic s July 1997 SMC System Memory Controller DATA SHEET D e s c r ip t io n The STP3020 System M em ory controller SMC interfaces to an array of DRAM and VRAM SIMM s. It acceler­ ates graphics and im aging to m ain memory and fram e buffers. It also provides the interface for video I/O

SuperSPARC

Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Contextual Info: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys­

Contextual Info: R E V IS IO N S E C NO C Y 1A -515A DATE 2 0 1 3 /0 8 /3 C REV J D E S C R IP T IO N CHANGE THE LABELING CONTENT FOR PRODUCTS T R A N S F E R TO PHILIPPINES C Y 1 2 -5 3 0 1 2 0 1 3 /0 9 /1 2 K CHANGE THE LABELING CONTENT FOR PRODUCTS T R A N S F E R TO PHILIPPINES

22-pin connector

Contextual Info: SEE NOTE WEEK CODE S EE DETAIL C >< X < < s 2 LTJ fn m r* I [O [□ tn 3.144 ± 0.03 58.8 MAX.) 2.3 UMAX.) 0.309(REF.) 0.6KMAX.) -LENGTHtSEE TABLE) DVI_A/D(M) CKT 14 BACK SIDE DETAIL A 8874 1-9020 D V I_I-D V I_I A/D CABLE 5M BLK 50 0 ± 150 PARCHMENT WHITE

DVI-D cable

Abstract: dvi dual link D 24 1 PVC DUROMETER dvi CABLE CONNECTION DIAGRAM DVI dual link connector Dvi CONNECTION DIAGRAM DVI to DVI CABLE CONNECTION DIAGRAM MOLEX 24 pin
Contextual Info: SEE NOTE 1.1 PIN 16 PIN 9 PIN 17 PIN 24 •DETAIL B DETAIL A- DETAIL A DETAIL B cxxx ^ W E E K NO.FOR YEAR. YEAR NO. "C"FOR MOLEX CHINA DETAIL C 8874I-8I2I DVI.D-DVI.D DUAL LINK CABLE 5M PARCHMENT WHT 8874 l-B 111 DVI.D-DVI.D DUAL LINK CABLE 3M PARCHMENT WHT

lg 6 pin cable

Abstract: EIA-364-41 CONDITION A
Contextual Info: C4 PIN 16 PIN 24 PIN 17 DETAIL B C5 I5.5 MAX. 0 .6 KMAX.) 0 .3 0 9 ( R E F . ) DVI_A(M) D E T A IL CKT 14 DETAIL cxxx WEEK NO. FOR Y E A R . •YEAR NO. -"C" FOR MOLEX CHINA DETAIL C 8874 1-8221 D V I_A -D V I_A ANALOG C A B LE A S S 'Y 5M PARCHMENT WHT 8874 1-8211

DVI to vga CABLE CONNECTION DIAGRAM

Abstract: VGA to vga CABLE CONNECTION DIAGRAM VGA CABLE CONNECTION DIAGRAM VGA 15 PIN CABLE CONNECTION DIAGRAM 15 pin VGA to dvi CABLE CONNECTION DIAGRAM 13 pin vga cable connection I-8320 VGA 20 PIN CABLE CONNECTION DIAGRAM DVI D cable ANALOG DVI 1 to vga CABLE CONNECTION DIAGRAM
Contextual Info: DETAIL cxxx 4 Í_ WEEK NO.FOR YEAR. •YEAR NO. -"C" FOR MOLEX CHINA DETAIL C 8874 I-8321 DVI.A-VGA CABLE ASS'Y 5M PARCHMENT WHT 8874 I-83 11 DVI.A-VGA CABLE ASS'Y 3M PARCHMENT WHT 8874 I-8301 DVI.A-VGA CABLE ASS'Y 2M PARCHMENT WHT 8874 I-8320 DVI.A-VGA CABLE ASS'Y 5M BLK

EK117

Abstract: EK119 23d14 sun SPARC 50 EL B17 D126D P3020
Contextual Info: STP3020 SPA RC T echrdogy Business Novem ber 1994 ST P 3020 DATA SHEET D System Memory Controller escription The STP3020 System Memory controller SMC interfaces to an array of DRAM and VRAM SIMMs. It accelerates graphics and imaging to main memory and frame buffers. It also provides the interface for

D2396

Abstract: D-74211 MAD44 ROE capacitor 220 SMC 2060 D101 D102 D112 STP3020 ROE capacitor F5 90
Contextual Info: STP3020 July 1997 SMC System Memory Controller DATA SHEET DESCRIPTION The STP3020 System Memory controller SMC interfaces to an array of DRAM and VRAM SIMMs. It accelerates graphics and imaging to main memory and frame buffers. It also provides the interface for video I/O

mrd 14b

Abstract: ba1643
Contextual Info: • 5 3 0 4 0 0 4 O O l E S L b 07^ L L C L64862 Mbus to Sbus Interface MSI Technical Manual Publication ID: M 14023 Publication Date: October 1, 1992 Company: L S I LOGIC CORP This title page is provided as a service by Inform ation Handling Services and displays

M-BD58

Abstract: OZ862AS PC97551 sd diode mx c425 BANIAS 15 pin D-SUB oBD quanta quanta computer AAD22 MBD58
Contextual Info: 5 4 3 NR1 MLB Block Diagram 2 1 01 CPU BANIAS CPU&NB Thermal Sensor u-FCPGA 478PIN D D FSB 4X100MHZ CRT CRT DDC2B 1x D-SUB 15-Pin Memory DDR400 NB 3200MB/s LCD 2x LVDS 1x SXGA+ ATI RS300MB 2x SODIMM NTSC/PAL TV-Out 596 BGA 1x 3.5 Jack A-LINK 66MHZ C HDD ATA

IT8512

Abstract: Sis 968 RTS5158 sis m672 G1410 SiSm672 sis 307elv sis307elv sis*307elv ME2N7002E
Contextual Info: 5 4 3 2 1 B test Modification P6. Prepare R502,C615 footprint and change R146 to 0603 for EMI request DACAVDD1 change source to VCC1.8 through a 3.3 ohm resistor R488 to solve CRT ripple issue D C P29. CON3 KB pin define follow PB2 Swap CP1,CP5,CP6,CP3,CP2,CP4 for layout smooth

sba20

Abstract: mbus master circuit
Contextual Info: S un M icro electro nics July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and con­ trols access to the 1 /O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem

TAZ BI-DIR

Abstract: Mbus master 250 slave circuit STP2103 MAD32
Contextual Info: S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive inter­

Contextual Info: Prelimina: SIARCTechnology STP1090A Business January Multi-Cache Controller ,TM DATA. SE ET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1090A is a high-perform ance external cache controller for the STP1020A SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used w hen a large secondary cache or an interface

STP2013

Abstract: Mbus master 250 slave circuit STP2013PGA-50 m-bus mbus STP2011 STP2013PGA50 MAD44
Contextual Info: STP2013PGA-50 July 1997 EMC DATA SHEET Error-Correcting Memory Controller DESCRIPTION The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive interrupts. Satellite state machines are granted execution by the arbiter in response to a buffered request. Stalled

dfp cable

Abstract: DFP 20 PIN to dvi diagram digital clock ckt diagram dfp 20 pin MDR 14 pin molex mx DVI-D to MDR digital mdr-20 DFP mdr-20 SD-88741-007
Contextual Info: -PIN 8 PIN 16PIN 24- V ti / ’ ui Ç 5i L g Ja fff DETAIL in V tsi r S < B oi K ^ ^— PIN 1 7.85ÍREF. 0.309 REF.) 0.6(MAX.) 0.531MAX.) DVI_D(M) DFP(M) CKT DETAIL A B ACK SIDE 5000 ± 150 PARCHMENT WHITE 887808287 196.9 ± 5.9 3000 ± 80 PARCHMENT WHITE 887808287

dvi-i CABLE CONNECTION DIAGRAM

Contextual Info: SEE NOTE I PIN 9 PIN 17 —; ‘”5 X X < < rn □ a -*• u! ^ in CD m m 0.309IR EF.) 0 .6 UMAX.) D V I_A /D M ) CKT 14 DETAIL DETAIL B cxxx ^ W E E K NO.FOR YEAR. YEAR NO. "C" FOR MOLEX CHINA DETAIL C 8 8 7 4 1-9021 D V I .I - D V I. I A /D CABLE 5M IVORY

BCM5787

Abstract: SB460 ATI SB460 PC638 PC618 PC87541 X235 C556B IOPLLVDD18 PC627
Contextual Info: 5 4 3 NR3a CPU 2 1 01 CPU Thermal Sensor Yonah / Merom BlOCK DIAGRAM NB Thermal Sensor u-FCPGA 478PIN D FSB D Battery 667 MHZ Dual channel Memory DDRII 667 SO-DIMM STANDARD ON BOARD 256MB SO-DIMM REVERSE PRIMARY HDD DC In DDR II CHANNEL A CRT DDC2B NB DDR II CHANNEL B

c1295 battery

Abstract: ipod touch circuit diagram TPM infineon SLB 9635 TT NEC C1181 nec c1251 Mx612 PC87541 AC45 RS600ME BE-34
Contextual Info: 5 4 3 CPU WR1G2 2 1 01 CPU Thermal Sensor Merom u-FCPGA 479PIN NB Thermal Sensor 3,4 ICS 951461 FSB D 667 MHZ (14) Memory Dual channel ON BOARD 256MB SO-DIMM NORMAL (10) SO-DIMM NORMAL ON BOARD 256MB (12) (11) HDD_PRIMARY DRIVE DDR II CHANNEL A CRT DDC2B

Contextual Info: S T P 2 Û1 3 P G A -50 S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting M emory Controller D e s c r ip t io n The STP2013 Error-C orrecting M em ory C ontroller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request m asters, w hile m onitoring periodic refresh and VIO preem ptive inter­

K 176 LE, K 561 LN

Abstract: AF34AG cn/A/U 237 BG
Contextual Info: Prelim inary SP A R C Business STP1020 A T ech n d o g y June 1995 S u p er S P A R C DATA SHEET TM Highly Integrated 32-Bit RISC Microprocessor D escription The STP1020A is a new member of the SuperSPARC family of microprocessor products. Like its pre­ decessors STP1020N and ST PI 020 this new part is fully SPARC version 8 compliant and is completely

TMx390

Abstract: SuperSPARC STP1020 STP1021A MAD19 STP1091 ADDR02 Mbus master 250 slave circuit stp1090 imad-26
Contextual Info: STP1091.frm Page 97 Monday, August 25, 1997 3:08 PM STP1091 July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC DESCRIPTION The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus system is required.

Contextual Info: STP3020 S un M ic r o e l e c t r o n ic s J u ly 1997 SMC System Memory Controller DATA SHEET D e s c r ip t io n The STP3020 System M em ory controller SMC interfaces to an array of DRAM and VRA M SIMM s. It acceler­ ates graphics and im aging to m ain m em ory and fram e buffers. It also provides the interface for video I/O