STP201 Search Results

STP2012

Abstract: SuperSPARC STP2016QFP
Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

Contextual Info: STP2012QFP S un M ic r o e l e c t r o n ic s J u ly 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DM A access to one AM D Am 7990 Local Area N etw ork Control­

STP2016

Abstract: SuperSPARC mbus 10 application STP2011 STP2016QFP mbus MCLK11 MOSC STP2012
Contextual Info: STP2016 July 1997 Clock-2 Generator System Clock Generator DATA SHEET DESCRIPTION The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

mbus 10 application

Abstract: STP2012 TP2018
Contextual Info: S un M icroelectronics July 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing

Contextual Info: S un M icro electro nics July 1997 MSBI DATA SHEET MBus to SBus Interface D e s c r ip t io n The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for

STP2012QFP

Contextual Info: STP 2Û 12Q FP S un M ic r o e le c tr o n ic s July 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AM D Am 7990 Local Area N etw ork Control­

STP201

Contextual Info: SPA RC T echrdogy Business N ovem ber 1994 S T P 2016 DATA SHEET D C lo c k s G e n e ra to r escription The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multi­

53C90A

Abstract: ncr53c90 STP2012 53C90 AD12 AM7990 STP2013 EIRQ15 STP2011 53c90 scsi
Contextual Info: STP2012QFP July 1997 DMA2 DATA SHEET SBus DMA Controller DESCRIPTION The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Controller for the Ethernet (LANCE), one NCR 53C90 SCSI controller (ESP), and one programmable Centronics-type parallel port. The

STP2014

Abstract: MK48T08-1 EBA11 STP2104 AmZ8 AD27 AD29 AD30
Contextual Info: STP2014.frm 1 Mon Jul 7 08:25:34 1997 STP2014 July 1997 SEC DATA SHEET SBus-to-EBus Controller DESCRIPTION The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the interrupt control and steering logic, the timer/counter registers, reset logic, and miscellaneous registers. The

sba20

Abstract: mbus master circuit
Contextual Info: S un M icro electro nics July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and con­ trols access to the 1 /O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem

IS279

Abstract: mbus master circuit
Contextual Info: S T P 2 0 1 1 P G A -5 0 S un M ic r o e le c t r o n ic s July 1997 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem.

TAZ BI-DIR

Abstract: Mbus master 250 slave circuit STP2103 MAD32
Contextual Info: S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive inter­

Contextual Info: S T P 2 0 1 1 P G A -5 0 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 MSI DATA SHEET MBus-to-SBus Interface D e s c r ip t io n The STP2011 M Bus-to-SBus Interface MSI provides an interface betw een the M Bus and the SBus and con­ trols access to the I / O subsystem. The M SI consists of two m ain functional blocks: the M em ory Subsystem

Contextual Info: STP2014 S un M ic r o e l e c t r o n ic s July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­

M-BUS

Contextual Info: S un M ic r o e l e c t r o n ic s July 1997 MSBI MBus to SBus Interface DATA SHEET D e s c r ip t io n The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for multiprocessing (MP),

Contextual Info: S T P 2 Û1 3 P G A -50 S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting M emory Controller D e s c r ip t io n The STP2013 Error-C orrecting M em ory C ontroller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request m asters, w hile m onitoring periodic refresh and VIO preem ptive inter­

D37M

Contextual Info: STP2013PGA-50 S un M ic r o e l e c t r o n ic s J u ly 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting M em ory Controller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request masters, while m onitoring periodic refresh and VIO preem ptive inter­

Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1 9 9 7 Clock-2 Generator System Clock Generator DATA SHEET D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for com ponents on the SBus and MBus. The M Bus and SBus are used by SPARC processors, such as SuperSPARC™. The M Bus is designed for multiprocessing

mbus master circuit

Abstract: STP2011 MAD44 mbus 10 application three phase ESC circuit diagrams MAD50
Contextual Info: STP2011PGA-50 July 1997 MSI DATA SHEET MBus-to-SBus Interface DESCRIPTION The STP2011 MBus-to-SBus Interface MSI provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem.

STP2018TAB

Abstract: STP2018 m-bus
Contextual Info: STP2018 July 1997 MSBI MBus to SBus Interface DATA SHEET DESCRIPTION The STP2018 MBus to SBus Interface MSBI provides a bus bridge between two different busses used by a number of SPARC microprocessors and controls access to the I/O subsystem. The MBus is designed for multiprocessing (MP),

STP2014QFP

Contextual Info: STP2014.frm 1 Mon Jul 7 08:25:34 1997 S un M e ic r o e l e c t r o n ic s J u ly 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/m ouse. The STP2014 also houses the inter­

SB013

Abstract: STP2012 53c90 NCR
Contextual Info: S un M icro electro nics July 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Control­

E-BA8

Abstract: ISOS refer STP2104
Contextual Info: S un M ic ro electro nics July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­

Contextual Info: STP2018 S un M ic r o e l e c t r o n ic s J u ly 1997 MSBI MBus to SBus Interface DATA SHEET D e s c r ip t io n The STP2018 M Bus to SBus Interface MSBI provides a bus bridge betw een two different busses used by a num ber of SPARC m icroprocessors and controls access to the I /O subsystem. The M Bus is designed for