MAX3892 Search Results

qfn-44 PACKAGE footprint

Contextual Info: KIT ATION EVALU E L B AVAILA 19-2215; Rev 6; 10/07 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO

155.52MHZ vcxo

Abstract: multiplexer transponder
Contextual Info: Design Note: HFDN-19.0 Rev 0; 03/02 2.7Gbps Transponder Applications using the MAX3892, MAX3882*, and MAX3670 Chipset *The MAX3882 will be available in the spring of 2002. MAXIM High-Frequency/Fiber Communications Group Maxim Integrated Products 4hfdn190.doc 03/05/2002

EFJohnson 131-1701

Abstract: MAX3892 MAX3892EVKIT MAX4429ESA
Contextual Info: 19-2257; Rev 0; 12/01 MAX3892 Evaluation Kit Features ♦ 3.3V Single Supply ♦ Selectable Reference Clock Frequencies: 622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz 666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz ♦ Selectable Parallel Input Clock Rate: 622.08MHz/311.04MHz, 666.51MHz/333.26MHz

Contextual Info: 19-2215; Rev 2; 3/06 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO allows for any static delay between the parallel output

Contextual Info: KIT ATION EVALU E L B AVAILA 19-2215; Rev 6; 10/07 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO

MAX3273

Abstract: MAX3882 MAX3892 MAX3892EGH 1024EP
Contextual Info: KIT ATION EVALU E L B AVAILA 19-2215; Rev 6; 10/07 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO

slbp

Abstract: slbo MAX3273 MAX3882 MAX3892 MAX3892EGH 666Hz
Contextual Info: 19-2215; Rev 1; 5/03 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO allows for any static delay between the parallel output

Contextual Info: 19-2215; Rev 5; 2/07 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO allows for any static delay between the parallel output

42EP

Contextual Info: 19-2215; Rev 3; 6/06 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO allows for any static delay between the parallel output

C11-C20

Abstract: MAX3892 MAX3892EVKIT JU-25 JU25 max4429
Contextual Info: 19-2257; Rev 1; 3/06 MAX3892 Evaluation Kit The MAX3892 evaluation kit EV kit is an assembled surface-mount demonstration board that provides easy evaluation of the MAX3892 2.7Gbps 4:1 serializer with clock synthesis and low-voltage differential signal (LVDS) inputs.

vco with opamp

Abstract: GR-253-CORE MAX3273 MAX3670 MAX3861 MAX3864 MAX3882 MAX3892 OC48 oc48 transponder
Contextual Info: Design Note: HFDN-19.0 Rev.1; 04/08 2.7Gbps Transponder Applications using the MAX3892, MAX3882, and MAX3670 Chipset Maxim Integrated Products 2.7Gbps Transponder Applications using the MAX3892, MAX3882, and MAX3670 Chipset 1 Introduction The MAX3892 and MAX3882 work together to

RST10

Abstract: GPON OLT OLT block diagram GPON GPON olt block diagram
Contextual Info: 19-3818; Rev 0; 9/05 KIT ATION EVALU E L B AVAILA 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications The MAX3634 burst-mode clock phase aligner CPA is designed specifically for 622Mbps or 1244Mbps GPON (ITU G.984) optical line terminal (OLT) receiver applications. The MAX3634 provides clock and clock-aligned

Contextual Info: 19-2166; Rev 1; 5/03 Low-Jitter 155MHz/622MHz Clock Generator Features ♦ Single +3.3V or +5.0V Supply ♦ Power Dissipation: 150mW at +3.3V Supply ♦ External VCO Center Frequencies fVCO : 155MHz to 670MHz ♦ Reference Clock Frequencies: fVCO, fVCO/2,

vco with opamp

Abstract: MAX3670 MAX3670EGJ MAX3892
Contextual Info: 19-2166; Rev 0; 9/01 Low-Jitter 155MHz/622MHz Clock Generator Features ♦ Single +3.3V or +5.0V Supply ♦ Power Dissipation: 150mW at +3.3V Supply ♦ External VCO Center Frequencies fVCO : 155MHz to 670MHz ♦ Reference Clock Frequencies: fVCO, fVCO/2,

FSLB2520-330K

Abstract: MAX3863 MAX3863EGJ maxim 1786
Contextual Info: 19-2281; Rev 4; 11/08 2.7Gbps Laser Driver with Modulation Compensation The MAX3863 is designed for direct modulation of laser diodes at data rates up to 2.7Gbps. An automatic power-control APC loop is incorporated to maintain a constant average optical power. Modulation compensation is available to increase the modulation current in

666Hz

Contextual Info: 19-2215; Rev 0; 11/01 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis Operating from a single 3.3V supply, this device accepts low-voltage differential-signal LVDS clock and data inputs for interfacing with high-speed digital circuitry, and delivers current-mode logic (CML) serial

BP25

Abstract: HFAN02
Contextual Info: 19-2247; Rev 0; 10/01 2.5Gbps Laser Driver with Automatic Modulation Control Features ♦ Single +3.3V or +5V Power Supply ♦ 68mA Supply Current ♦ Up to 2.5Gbps NRZ Operation ♦ Feedback Control for Constant Average Power ♦ Feedback Control for Constant Extinction Ratio

Contextual Info: 19-2281; Rev 0; 1/02 2.7Gbps Laser Driver with Modulation Compensation The MAX3863 accepts differential CML clock and data input signals with on-chip 50Ω termination resistors. If a clock signal is available, an input data-retiming latch can be used to reject input pattern-dependent jitter.

Contextual Info: 19-2718; Rev 2; 4/09 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Features The MAX3882A is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps serial data to 4-bit-wide, 622Mbps

vco with opamp

Abstract: 19Hz
Contextual Info: 19-2697; Rev 0; 12/02 Low-Jitter 155MHz/622MHz Clock Generator Features ♦ Single +3.3V or +5.0V Supply ♦ Power Dissipation: 150mW at +3.3V Supply ♦ External VCO Center Frequencies fVCO : 155MHz to 700MHz ♦ Reference Clock Frequencies: fVCO, fVCO/2,

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

CSBLA614KJ58

Abstract: NX3225da CSTLA4M00G55-B0 CSTCV12M0T54J-R0 CSTCV11M0T54J-R0 CSBLA400KJ5E-B0
Contextual Info: SECTION INDEX CERAMIC RESONATORS Boxed, 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . 229 Dipped, 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . 230 Surface Mount, 2 Terminal . . . . . . . . . . . . . 231-232 Dipped, 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . 233

GPON olt block diagram

Abstract: gpon optical line termination GPON OLT OLT block diagram GPON GPON ONT block diagram gpon MAX3634 MAX3656 MAX3738 MAX3864
Contextual Info: 19-3818; Rev 0; 9/05 KIT ATION EVALU E L B AVAILA 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications The MAX3634 burst-mode clock phase aligner CPA is designed specifically for 622Mbps or 1244Mbps GPON (ITU G.984) optical line terminal (OLT) receiver applications. The MAX3634 provides clock and clock-aligned

vco with opamp

Abstract: MAX3670 MAX3670EGJ MAX3892 ic op amp
Contextual Info: 19-2166; Rev 2; 9/09 Low-Jitter 155MHz/622MHz Clock Generator Features The MAX3670 is a low-jitter 155MHz/622MHz reference clock generator IC designed for system clock distribution and frequency synchronization in OC-48 and OC-192 SONET/SDH and WDM transmission systems. The