MAX924 Search Results

MAX9217

Abstract: MAX9247 MAX9248 MAX9250
Contextual Info: 19-3943; Rev 3; 4/09 KIT ATION EVALU LE B A IL A AV 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

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Abstract: MAX9217 MAX9247 MAX9248 MAX9250 MAX9250ECM
Contextual Info: 19-3943; Rev 2; 5/08 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 1; 10/06 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

D4S20F-40MA5-Z

Abstract: MAX9249 C1005X5R0J CDM20600 MAX9260 ROSENBERGER* usb R524 GRM188R71C106K diode U12 c530 EP3C25F324C8N
Contextual Info: 19-5177; Rev 0; 3/10 MAX9249 Evaluation Kit Features The MAX9249 evaluation kit EV kit provides a proven design to evaluate the MAX9249 gigabit multimedia serial link (GMSL) with spread spectrum and full-duplex control channel. The EV kit also includes Windows XPM-,

AN3964

Abstract: APP3964 MAX9218 MAX9247 MAX9248 MAX9250 PRBS
Contextual Info: Maxim > App Notes > AUTOMOTIVE CLOCK GENERATION AND DISTRIBUTION HIGH-SPEED SIGNAL PROCESSING Keywords: Test Mode, PRBS, MAX9247, LVDS Testing, Serializer HIGH-SPEED INTERCONNECT Dec 15, 2006 APPLICATION NOTE 3964 Enabling Test Modes on the MAX9247 Abstract: The MAX9247 features an internal test mode, which is useful for debugging the serial link or

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

DX 10 35 V

Abstract: d223 8 pin D223 7400DC MAX924 1 tr 235 VA228 1E-15 bf 238
Contextual Info: * MAX924 FAMILY MACROMODELS * -* FEATURES: * Ultra-Low Quiescent Current * 12uS Propagation Delay 10mV Overdrive * Input Voltage Range Includes Negative Supply * Internal 1.182V Reference * Available in 16-Pin DIP/SO/uMAX (Quad MAX924)

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 3; 2/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

APP4019

Abstract: MAX9213 MAX9214 MAX9217 MAX9218 MAX9247 MAX9248 AN4019 composite video to lvds
Contextual Info: Maxim > App Notes > AUTOMOTIVE HIGH-SPEED INTERCONNECT HIGH-SPEED SIGNAL PROCESSING Keywords: LVDS video interface, automotive video interface, LVDS interface, composite video baseband signal, CVBS, navigation display interface, LVDS for infotainment, MAX9213, MAX9214, MAX9217, MAX9218, MAX9247, MAX9248

20601c

Contextual Info: 19-0115: Rev3:3/95 y k i y j x i y i / i Ul t r a L o w - P o w er, Single/Dual-Supply C om para to rs _ G e n e r a l D e s c r i p t i o n Ideal fo r 3V or 5V sin g le -s u p p ly a p p lica tio n s, the MAX921-MAX924 operate from a single +2.5V to +11V

automotive ecu manual

Abstract: GT11L-2S max9249
Contextual Info: 19-5138; Rev 4; 1/12 TION KIT EVALUA BLE AVAILA Gigabit Multimedia Serial Link Serializer with LVDS System Interface The MAX9249 serializer with LVDS system interface utilizes Maxim’s Gigabit multimedia serial link GMSL technology. The MAX9249 serializer pairs with any

JP13

Abstract: MAX9217 MAX9218 MAX9247 MAX9248 MAX9250
Contextual Info: Maxim > App Notes > Automotive High-Speed Interconnect High-Speed Signal Processing Keywords: MAX9217, MAX9218, MAX9247, MAX9248, MAX9250 Jun 29, 2007 APPLICATION NOTE 4020 Working with MAX9217/MAX9218/MAX9247/MAX9248/MAX9250 Evaluation Boards Abstract: This application note describes how to prepare and use the evaluation boards for the MAX9217/

100mv

Abstract: MAX924
Contextual Info: * MAX924 SUPPLY CURRENT * 924IDD.CIR XAR1 3 2 7 4 6 MAX924 VP 7 0 5V VN 4 0 0V VIN 3 0 100mV *VIN 3 0 PULSE 100mV 100mV 2us 3N 3N 20us vshort 2 0 0mV rload 6 0 10000E+3 .OPTIONS RELTOL=.01 .TRAN 100nS 20us .PROBE .LIB MAX924.fam .END

100E3

Abstract: 100PF MAX924
Contextual Info: * MAX924 & REF RESPONSE TIME, SINGLE +5V SUPPLY * 924ref.CIR XAR1 3 2 7 4 6 MAX924 XAR2 7 4 235 REF VP 7 0 5V VN 4 0 0V VIN 3 0 PULSE 0mV +110mV 2us 3N 3N 20us vshort 2 0 100mV CLOAD 6 0 100PF rload 6 0 100E+3 .OPTIONS RELTOL=.01 .TRAN 100nS 20us .PROBE .LIB MAX924.fam

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

LVDS Serializer

Contextual Info: 19-3955; Rev 1; 9/06 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer The MAX9247 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial-data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial-data rate. The data-enable input determines

622k

Abstract: AX922 MAX921-924
Contextual Info: JV\JIXAJV\ 19-0115; Rev 1; 7/93 U ltra Low-Power, Single-fDual-Supply C om parators Ideal for 3V or 5V single-supply applications, the MAX921-MAX924 operate from a single +2.5V to +11V supply or a ± 1.25V to ±5V dual supply , and each com parator's input voltage range swings from the

Contextual Info: 19-5138; Rev 4; 1/12 TION KIT EVALUA BLE AVAILA Gigabit Multimedia Serial Link Serializer with LVDS System Interface The MAX9249 serializer with LVDS system interface utilizes Maxim’s Gigabit multimedia serial link GMSL technology. The MAX9249 serializer pairs with any

150pf 6kv

Abstract: MAX9242 MAX9242EUM MAX9246
Contextual Info: 19-3954; Rev 4; 7/09 KIT ATION EVALU E L B A AVAIL 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock

MAX924

Abstract: MAX934
Contextual Info: * MAX934 SUPPLY CURRENT * 934IDD.CIR XAR1 3 2 7 4 6 MAX924 * +IN -IN V+ V- OUT VP 7 0 5V VN 4 0 0V VIN 3 0 100mV *VIN 3 0 PULSE 100mV 100mV 2us 3N 3N 20us vshort 2 0 0mV rload 6 0 10000E+3 .OPTIONS RELTOL=.01 .TRAN 100nS 20us .PROBE .LIB MAX924.fam .END

MAX9242EUM

Abstract: MAX9242 MAX9246
Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock