MAX9386 Search Results

Contextual Info: 19-2617; Rev 1; 12/02 Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function on the MAX9386/ MAX9387. The MAX9388 has two select inputs, SEL0 and SEL1. The mux select inputs are compatible with

MAX9386

Abstract: MAX9386EEP MAX9386EUP MAX9387 MAX9388 MAX9388EUP MC100EP57
Contextual Info: 19-2617; Rev 1; 12/02 Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output VBB. All the differential inputs have internal bias

MAX9386

Abstract: MAX9386EEP MAX9386EUP MAX9387 MAX9388 MAX9388EUP MC100EP57
Contextual Info: 19-2617; Rev 0; 10/02 Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output VBB. All the differential inputs have internal bias

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

AN1916

Abstract: MAX9386 MAX9310 MAX9311 MAX9315 MAX9316 MAX9317 MAX9320 MAX9322 MAX9360
Contextual Info: Maxim > App Notes > HIGH-SPEED INTERCONNECT Keywords: jitter, gaussian, random, RJ, deterministic, cycle to cycle, adjacent cycle, duty cycle distortion, pulse width distortion, inter-symbol, bit error rate, BER, ber Mar 06, 2003 APPLICATION NOTE 1916 An Introduction to Jitter in Communications Systems