MC74AC10 Search Results

MC74ACT10N

Abstract: MC74AC10 MC74AC10D MC74AC10DR2 MC74AC10DT MC74AC10N MC74ACT10 MC74ACT10D MC74ACT10DR2
Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

74AC

Abstract: MC74AC10 MC74ACT10
Contextual Info: MC74AC10 MC74ACT10 Triple 3ĆInput NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 N SUFFIX CASE 646-06 PLASTIC 1 2 3 4 5 6 7 GND D SUFFIX CASE 751A-03 PLASTIC MAXIMUM RATINGS*

MC74AC573DTR2

Abstract: MC74ACT151D MC74ACT240DW MC74AC273DWR2
Contextual Info: CHAPTER 4 Index http://onsemi.com 295 FACT Device Index Device Number Page Device Number MC74AC00 Page 12 Device Number MC74AC10M 43 MC74AC151DT 80 MC74AC00D 12 MC74AC10N 43 MC74AC151DTR2 80 MC74AC00DR2 12 MC74AC11D 48 MC74AC151M 80 MC74AC00DTR2 12 MC74AC11DR2

948F

Abstract: MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N
Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.

AC10g

Abstract: "NAND Gate" 74AC MC74AC10 MC74AC10N MC74ACT10
Contextual Info: MC74AC10, MC74ACT10 Triple 3−Input NAND Gate Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs • Pb−Free Packages are Available http://onsemi.com PDIP−14 N SUFFIX CASE 646 VCC 14 13 12 11 10 9 8 14 1 SOIC−14 D SUFFIX CASE 751A

Contextual Info: M O TO R O LA MC74A C 109 MC74ACT109 D ual J K P o sitiv e Ed ge-Trig gered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of tw o high-speed completely Independent transition clocked JK flip-flops. The clocking operation is independent o f rise and

MC74AC10

Abstract: MC74AC10D MC74AC10DR2 MC74AC10DT MC74AC10N MC74ACT10 MC74ACT10D MC74ACT10DR2 MC74ACT10N
Contextual Info: MC74AC10, MC74ACT10 Triple 3−Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs w These devices are available in Pb−free package s . Specifications herein apply to both standard and Pb−free devices. Please see our website at

Contextual Info: M MOTOROLA MC74AC10 MC74ACT10 Product Preview T rip le 3 -In p u t N A N D G ate TRIPLE 3-INPUT NAND GATE • O u tp u ts Source/S ink 24 m A • 'ACT10 Has TTL C o m p a tib le Inputs N SUFFIX CASE 646*06 PLASTIC i D SUFFIX CASE 751A-02 PLASTIC DC CHARACTERISTICS

Contextual Info: MOTOROLA M C74A C 109 M C 74A C T109 Dual J K Positive Edge-Triggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of two high-speed completely Independent transition clocked JK flip-flops. Thej:locking operation Is independent of rise and fall

Contextual Info: MC74AC10 MC74ACT10 Triple 3ĆInput NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 13 12 11 10 9 1 2 3 4 5 6 8 TRIPLE 3-INPUT NAND GATE 7 GND Figure 1. Pinout: 14–Lead Packages Conductors Top View N SUFFIX CASE 646-06

AC10g

Abstract: Q1/AC10G
Contextual Info: MC74AC10, MC74ACT10 Triple 3−Input NAND Gate Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs • Pb−Free Packages are Available http://onsemi.com PDIP−14 N SUFFIX CASE 646 VCC 14 13 12 11 10 9 8 14 1 SOIC−14 D SUFFIX CASE 751A

Contextual Info: gl M O T O R O L A M C74AC109 M C 74A C T109 Dual J K Positive Edge-Triggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. T h ejtocking operation is independent of rise and fall

Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.

MC74AC10

Abstract: MC74AC10D MC74AC10DR2 MC74AC10DT MC74AC10N MC74ACT10 MC74ACT10D MC74ACT10DR2 MC74ACT10N
Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform.

Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP−14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO−14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14−Lead Packages Conductors

Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

Contextual Info: L M M OTOROLA M C74AC109 M C74ACT109 Dual JK Positive Edge-Triggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC102/74ACT109 consists of two high-speed com pletely independent transition clocked JK flip-flops. The_clocking operation is independent of rise and fall

948F

Abstract: MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N
Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop refer to

Contextual Info: b3b?252 OQTHBOG Ô2b « M O m bbE D MOTOROLA SC LOGIC MOTOROLA MC74AC109 MC74ACT109 Dual JK Positive Edge-TViggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The M C 74A C 10 9 /7 4 A C T 109 consists of tw o high-speed co m ple te ly independent

Contextual Info: MC74AC109 MC74ACT109 Dual JK Positive EdgeĆTriggered FlipĆFlop The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop refer to

Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

74AC

Abstract: MC74AC109 MC74ACT109
Contextual Info: MC74AC109 MC74ACT109 Dual JK Positive EdgeĆTriggered FlipĆFlop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall

MICRON RESISTOR cb 0229

Abstract: 2N2369 transistor pulse generator
Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors