MDIO PHY Search Results

MDIO clause 45 specification

Abstract: cortex read diagram cortex cpu ethernet mdio circuit diagram
Contextual Info: PSoC Creator Component Datasheet MDIO Interface 1.0 Features • MDIO Interface component to be used in conjunction with Ethernet products •    Configurable physical address Supports up to 4.4 MHz in the clock bus mdc Compliant with IEEE 802.3 Clause 45

LPC175x

Abstract: MDIO MDIO write MDIO MDC AN10859 AN1085 NXP Interface and Connectivity MDIO controller nxp lpc175x DP83848C
Contextual Info: AN10859 LPC1700 Ethernet MII Management MDIO via software Rev. 01 — 6 August 2009 Application note Document information Info Content Keywords LPC1700, Ethernet, MII, RMII, MIIM, MDIO Abstract This code example demonstrates how to emulate an Ethernet MII

1000BASE-T2

Abstract: MDIO clause 22 clause 22 phy registers wishbone RD1074 MDIO MDIO controller 3 to 8 bit decoder vhdl IEEE format LCMXO640C-4T100C 100Base-T2
Contextual Info: Accessing Control Registers Through the MDIO Bus February 2010 Reference Design RD1074 Introduction Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface SMI to transfer management data between an Ethernet Media

TX2C

Abstract: RD2 TP10 GT48300 gt-48300 GT-48310 TX3C 6r190 GT48310A CDATA14 gt48310
Contextual Info: A B C configuration rxd0[1:0] txd0[1:0] rxd7[1:0] txd7[1:0] e_cs e_clk e_di e_do endev* limit4 Test Points 4 rxd0[1:0] txd0[1:0] main_clk rst* txen[7:0] txen[7:0] 4 d_cs* d_we* d_ras* d_cas* d_DQM mdio mdc mdio mdc CRS_dv[7:0] d_data[31:0] d_addr[11:0] d_data[31:0]

MDIO

Abstract: ARM926EJ-S C6000 TMS320C6000
Contextual Info: TMS320DM646x DMSoC Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEQ6 December 2007 2 SPRUEQ6 – December 2007 Submit Documentation Feedback Contents Preface. 10

EMAC

Abstract: MDIO C6000 SPRU983 TMS320C6000
Contextual Info: TMS320DM643x DMP Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRU941A April 2007 2 SPRU941A – April 2007 Submit Documentation Feedback Contents Preface. 10

MDIO

Abstract: tms320c64x teardown C6000 TMS320C6000 54923
Contextual Info: TMS320C642x DSP Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEM6A April 2007 2 SPRUEM6A – April 2007 Submit Documentation Feedback Contents Preface. 10

QT2042

Abstract: qt2044 10GBASE-CX4 XGXS
Contextual Info: PRODUC T BRIEF 042 QT2 M QT2042/QT2044 3.125 Gb/s XAUI Physical Layer IC for 10GBASE-LX4 and 10GBASE-CX4 Applications Features Description • 10GE, 10GFC data rate support • Compliant to IEEE802.3ae standard, and XENPAK MSA • MDC/MDIO and EEPROM interface

MDIO

Abstract: ARM926EJ-S C6000 TMS320C6000
Contextual Info: TMS320DM644x DMSoC Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUE24A April 2007 2 SPRUE24A – April 2007 Submit Documentation Feedback Contents Preface. 10

VT6528

Abstract: 100BASE-X MDIO phy gvrp PHY 2078 ss smii MII switch "Spanning Tree"
Contextual Info: BLOCK DIAGRAM： Jumpers 2-pin EEPROM Initialization Controller MDCx, MDIO LED outputs PHY Management Interface LED Controller 8K+256 MAC Table 4K VLAN Table 1K Multicast Table 256 L2+ Rule/Action 4Mb Packet Buffer 4096x128-Byte Packet Buffer Management Unit

10GBASE-LR

Abstract: GR-468-CORE Optillion AB
Contextual Info: TOP 3010-SC 10 Gbit/s Ethernet XENPAK Transceiver 10GBASE-LR λ =1310 nm PRODUCT BRIEF KEY FEATURES • • • • • • • • • • • Complete integrated Ethernet PHY. True system ”Hot-Swappable”. Configurable through the MDIO. Extensive Built In Self-Test.

10BASET

Abstract: DP83223V DP83846A DP83846AVHG toa25 s558-5999-46
Contextual Info: DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver 2002 National Semiconductor Corporation www.national.com DP83846A RX_CLK RXD[3:0] RX_DV RX_ER CRS COL MDC MDIO TX_EN SERIAL MANAGEMENT TX_ER TX_CLK HARDWARE CONFIGURATION PINS AN_EN, AN0, AN1 (PAUSE_EN)

802.3 CRC32

Abstract: 81313 CRC-32 Gigabit Ethernet PHY MorethanIP ethernet mac 1588 PHY Ethernet to FIFO
Contextual Info: 1588 Tri-Speed Ethernet MAC Core Product Brief V1.0 – March 2006 MAC Receive Application Interface Transmit Application Interface Transmit FIFO Pause Frame Terminate TX Control CRC Gen. Pause Frame Generate Timestamping Configuration Statistics MDIO Master

SPRU401

Abstract: MDIO tms320c64x teardown C6000 SPRU189 SPRU190 TMS320C6000 SPRU628A
Contextual Info: TMS320C6000 DSP Ethernet Media Access Controller EMAC / Management Data Input/Output (MDIO) Module Reference Guide Literature Number: SPRU628A March 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

jabber

Abstract: 23Z128 TNETE2004 TNETX15VEPGE TNETX3150
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

10Gb Ethernet XGXS Core

Abstract: XGXS 8b/10b encoder MDIO MDC MDIO clause 45 ORT42G5 ORT82G5 ba rx
Contextual Info: 10Gb Ethernet XGXS Core July 2003 IP Data Sheet Features • 64-bit data/8-bit control packet generator/checker on the XGMII side that supports standard compliant CRPAT and CJPAT generation and checking for XAUI interoperability testing. • Standard compliant MDIO/MDC interface.

BCM8706

Abstract: 10G BIST PRBS 64b/66b encoder gearbox microcontroller optics fiber MDIO clause 45 XAUI 8706p 10G serdes 2.5 xaui
Contextual Info: BCM8706 XAUI TO SERIAL 10G BASE-LRM TRANSCEIVER SUMMARY OF BENEFITS FEATURES • Meets and exceeds industry standard • IEEE 802.3ae • IEEE802.3aq • MDIO interface compliant to IEEE 802.3ae Clause 45 with extended indirect address register access

jabber

Abstract: 23Z128 TNETE2004 TNETX15VEPGE TNETX3150
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

M06T

Abstract: 10BaseT-HD filmag
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

PH163539

Abstract: RJ8-45 DM9161A r0603 ph163539 -davicom F.B/120/S0603 47KX4 CE5MM 100uf 16V SOT R23 Y1 SOT-89
Contextual Info: 5 4 2 1 LINK PHY_LINKSTS TXER PHY_TXER D 3 D TXD3 TXD2 TXD1 TXD0 TXEN TXCLK PHY_TXD3 PHY_TXD2 PHY_TXD1 PHY_TXD0 PHY_TXEN PHY_TXCLK VCC3 VCC3 R23 RN2 1.5K R0603 LINK_ACT MDC MDIO MDC DVDD TXCLK/ISOLATE TXEN TXD0 TXD1 TXD2 TXD3 TXER/TXD4 DGND CABLESTS/LINKSTS

88X2010

Abstract: 88X2040 optical encoder module marvell IEEE 88X2011 88w2
Contextual Info: Transceiver Solutions Alaska X 10 Gigabit Ethernet and 10 Gigabit Fibre Channel LAN/WAN Transceivers 88X2010/88X2011 PRODUCT OVERVIEW MDC MDIO INTn L0_RXP/N L1_RXP/N L2_RXP/N L3_RXP/N L0_TXP/N L1_TXP/N L2_TXP/N L3_TXP/N 8B/10B Decoder FIFO 64B/66B Encoder

Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking

PIN assignments of UTP cables

Abstract: 23Z128 TNETE2004 TNETX15VEPGE TNETX3150
Contextual Info: TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023C – OCTOBER 1996 – REVISED MAY 1997 D D D D D D D D Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer PHY Interfaces in One Package Minimizing PCB Footprint for Internetworking