MERR INTEL Search Results

D52A

Contextual Info: DP8402A,DP8403,DP8404,DP8405 DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits EDAC's Literature Number: SNOSBX3A August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s)

HI-6121

Contextual Info: HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface SPI MIL-STD-1553 Remote Terminal ICs GENERAL DESCRIPTION “RoHS compliant” lead-free option is offered. REMOTE TERMINAL FEATURES • Fully integrated 3.3V Remote Terminal meets all

HI-6120

Abstract: Holt 1553 Controller - HI6110 HI-6121 HOLT INC 00FF motorola mc17 MIL-STD1760 6121 HOLT
Contextual Info: November 2009 HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface SPI MIL-STD-1553 Remote Terminal ICs GENERAL DESCRIPTION REMOTE TERMINAL FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic

HI6120P

Contextual Info: HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface SPI MIL-STD-1553 Remote Terminal ICs GENERAL DESCRIPTION The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are

HI-6121

Abstract: hi6121
Contextual Info: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a

PM-DB2776

Abstract: hi6121 35BUSA transformer coupling mil-std1553 PM-DB2762
Contextual Info: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a

Contextual Info: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a

HI-6110

Abstract: Holt 1553 Controller HI6110 HOLT INC Holt 1553 Controller - HI6110 HI-6121 HI-6120 hi6121 0x0043 DS6120 MIL-STD-1553B
Contextual Info: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a

Contextual Info: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a

Contextual Info: FEATURES The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a

MDX-L

Abstract: M020 m043 M062 MD10 MD14 MD22 AS6364
Contextual Info: 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTIONORCINT _D 33121 FEBRUARY 1 9 9 0 -R E V IS E D S EP TE M B E R 1990 12-ns Max Pass-Thru Operation When Used in Correct-Only-On-Error Configurations 17 X 17 GA PACKAGE {TOP VIEW 8 Detects and Corrects Single-Bit Errors

LR3000

Abstract: LR3000A
Contextual Info: Chapter 3 LR3202A L-Bus Controller This chapter describes the LR3202A L-Bus Controller. Chapter 3 is organized into these sections: • General Description ■ Configuring the LR3202A ■ Programming the System Control Registers ■ Signal Definitions ■ L-Bus Operation

Contextual Info: HI-6130 / HI-6131 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • Two options are offered for host access to internal registers and static RAM: The HI-6130 uses a 16-bit parallel bus; the HI-6131 communicates with the host

IRIG B generator

Abstract: lm 16151 HI-6131 HI-6130 DS6130 pin diagram for IC 1619 30 pin HI-6132 TT32 digital timer IRIG B 122 generator 0x02FE
Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

EK117

Abstract: EK119 23d14 sun SPARC 50 EL B17 D126D P3020
Contextual Info: STP3020 SPA RC T echrdogy Business Novem ber 1994 ST P 3020 DATA SHEET D System Memory Controller escription The STP3020 System Memory controller SMC interfaces to an array of DRAM and VRAM SIMMs. It accelerates graphics and imaging to main memory and frame buffers. It also provides the interface for

Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

k535

Abstract: CDB22 LR3000 cxl tuner diagram interfacing of memory devices with 8086 LB1K LR3202A LR3203 LR3205 LR32D04
Contextual Info: Chapter 3 LR3202A L-Bus Controller This chapter describes the LR3202A L-Bus Controller. Chapter 3 is organized into these sections: • General Description ■ Configuring the LR3202A ■ Programming the System Control Registers ■ Signal Definitions ■ L-Bus Operation

IRIG B generator

Abstract: HI-6131 IRIG B 122 generator lm 16151 IRIG-106 BT 2323 M ic pin configuration 80HEX Holt 1553 Controller HI6110 mc16 TSR16
Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

Contextual Info: HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCPIPTION • The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains

str f 6167

Abstract: amz8127 str 6167 supi 3 ls z80b Am8001 AM8163 IC HS 8167 z80 multibus 74LS240
Contextual Info: Am8163/Am8167 A m 8 1 6 3 /A m 8 1 6 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

79R3020

Abstract: 7 bit hamming code practical application of parity generator 49C466 R3000 processor error monitor comparator multiplexer parity error multiplexer parity comparator IDT49C466 49C465 R3000
Contextual Info: ERROR DETECTION AND CORRECTION WITH IDT49C466 APPLICATION NOTE AN-94 APPLICATION NOTE AN-94 ERROR DETECTION AND CORRECTION WITH IDT49C466 Integrated Device Technology, Inc. By Anupama Hegde INTRODUCTION ERROR DETECTION AND CORRECTION WITH It is widely accepted that system failures and down time THE 49C466