MICRON CMOS 1988 Search Results

i8237A

Abstract: i8237 i8259a 68C45 Z80 CRT controller micron cmos 1988 interface 8254 with 8086 8086 structure block diagram of 8086 and 8088 M85C30
Contextual Info: V L S I TECHNOLOGY INC IflE D H P V L S I T ech n o lo gy, inc. • T3flfl347 0D0324L. S ■ t- ^ VMC10 AND VMC100 SERIES 2-MICRON AND 1.5 MICRON ADVANCED CMOS MEGACELL FAMILY FEATURES FAMILY DESCRIPTION ASIC COMPATIBLE • Library of m icroprocessor peripheral functions

Contextual Info: SYSTEMS SLA8000 Series June 1988 VERY HIGH SPEED CHANNELLESS CMOS GATE ARRAYS D escription The SLA8000 Series consists of a group of seven very high-speed, sea-of-gates CMOS gate arrays. The series is fabricated utilizing our state-of-the-art 1.2 micron sili­

PD65000

Abstract: 8748 NEC CMOS-5 NEC nec 8748 94Q3 NEC CMOS-4
Contextual Info: SEC CMOS-5 1.2-MICRON CMOS GATE ARRAYS NEC Electronics Inc. PRELIM INARY Description The CM O S-5 gate arrays are low -pow er, high-speed integrated circu its fea tu ring 1.2-m icron silicon -ga te CMOS technology. The basic cell on the gate array chip consists o f six transistors, three p-channel and

IMS1400M

Abstract: IMS1403LM IMS1403M IMS1403M-45 16kx1 static ram IMS1400
Contextual Info: IMS1403M IMS1403LM CMOS High Performance 16K x 1 Static RAM MIL-STD-883C FEATURES DESCRIPTION • INMOS1Very High Speed CM OS • Advanced Process -1 .6 Micron Design Rules • Specifications guaranteed over full military temperature range -55° C to +125° C

80386 microprocessor functional block diagram

Abstract: block diagram of 80386 microprocessor intel 80386 motherboard, IOAIO intel 80386 block diagram pinout 80386 80386 microprocessor block diagram and pin diagram intel 80386 pin diagram 80386 pin configuration pin of microprocessor 80386
Contextual Info: Advance Information FE6022 Address And Data Buffer Devices □ □ □ Provides Address and Data Buffos that interface to the Micro Channel * Meets Micro Channel AC/DC Specifications Contains Peripheral Bus Address and Data Buf­ fos □ Low Power 1.25 Micron CMOS Technology

VGT200

Abstract: full subtractor circuit using decoder and nand ga
Contextual Info: VLSI T ec h n o lo g y , in c . VGT200 SERIES CONTINUOUS GATE TECHNOLOGY 1.5-MICRON GATE ARRAY SERIES FEATURES DESCRIPTION • Available in thirteen sizes from 960 to 54,000 usable gates The VGT200 Series is an advanced, high performance CMOS gate array

Contextual Info: FLEX 8000 Programmable Logic Device Family February 1993, ver. 1 Features Data Sheet ^ □ □ □ □ □ □ □ □ □ □ High-density, register-rich programmable logic device family 4,000 to 24,000 usable gates 452 to 2,252 registers Fabricated on a 0.8-micron CMOS SRAM technology

S-MOS navnet

Abstract: S-MOS asic B16c F1841
Contextual Info: DEC 2 3 i32S _ S-MOS S Y S T E M S • ■ ASIC _ A Seiko Epson Affiliate SLA9000 OCTOBER 1990 HIGH SPEED CMOS GATE ARRAYS DESCRIPTION The S-MOS SLA9000 series is a family of sea-of-gates • 1.0 micron drawn channel length N-Channel

LI26

Abstract: ISP9119 ISP9119CN44 ISP9119CPL ISP9119IDL ISP9119IN44 ISP9119IPL ISP9119MDL
Contextual Info: ISP9119 GE Solid State FIFO RAM Controller GENERAL DESCRIPTION FEATURES The ISP9119 FIFO RAM Controller FRC , together with a static RAM array, forms a First-In-First-Out (FIFO) buffer. The ISP9119 FRC, implemented in Intersil’s 1.5 micron AVLSI CMOS technology, is a pin for pin compatible re­

B8228

Contextual Info: kfoEC S 6 Í?9C S-MOS S Y T E M ASIC S Preliminary A Seiko Epson Affiliate SLA10000 AUGUST 1990 HIGH SPEED CMOS GATE ARRAYS DESCRIPTION FEATURES The S-MOS SLA10000 series is a channeMess gate • .76 micron drawn channel length N-Channel array manufactured on S-MOS’ state-of-the-art 0.8

TTL 7466

Abstract: B8530 SLA909P SLA9000PIUS S-MOS navnet 936p T374H A161H F144-8 octal p-channel ARRAY
Contextual Info: S-Î1 0 S SYSTEMS INC SbE D • OQOlSlb 331 « S Î I O SLA9000PIUS Series CMOS HIGH SPEED GATE ARRAYS ■ DESCRIPTION The S-MOS SLA9000Plus series is a family of sea-of-gate arrays manufactured on S-MOS’ state-of-the-art 1.0 micron double-metal SiCMOS process. This series has been designed for high I/O, medium gate count designs

T157WG

Abstract: S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE
Contextual Info: S-M 0 S S Y S T E M S INC 5bE J> m 7 ci3 Z eÏQ'l GG01522 fc.35 H S I 1 0 SLA1 OOOO Series HIGH SPEED CMOS GATE ARRAYS • DESCRIPTION The S-MOS SLA10000 series is a channel-less gate array manufactured on S-MOS’ state-of-the-art 0.8 micron double-metal SiCMOS process. The series consists of 11 arrays ranging from 9,000 to 101,800 usable gates and

1kx1 static ram

Abstract: 80c85 S6504 A10 dual operational cmos ttl level shifter S6532 S3374 s7616
Contextual Info: HARRIS SEflICOND SECTOR i-/lyu/il t i j IfaE D • 43 05271 OOlSlTfl b ■ HS-65641/44/45RH HS-65646/48RH HARRIS PREVIEW Radiation Hardened Asynchronous 64K SOI CM O S Static RAM Family May 1988 Features • 1.2 Micron Radiation Hardened SOI CM O S 1 X106RAD Si

2500ECL

Abstract: Motorola Bipolar Power Transistor Data Double Die IC 566 function generator HCA62A17 CMOS 4032 1987 Micron Technology Micron NAND bca 1st motorola ECL motorola mca
Contextual Info: BR334/D Rev 3 Motorola Semicustom gives the designer the same process-technology choices available for discrete-logic designs, and the option of Macrocell array or cell-based func­ tions for commercial and military applications. • For very high speeds — state-of-the-art ECL arrays.

MT8880AC

Abstract: MT8870CE MT8880CE MT8870C JEDEC-22BA102 cd200 mt8870 example code 87Q4 MT8870C-1 MT88L70
Contextual Info: MITEL SEMICONDUCTOR RELIABILITY MONITORING PROGRAM 1996 Table of Contents 1 INTRODUCTION TO MITEL RELIABILITY MONITORING . 1-1 2 RELIABILITY MONITOR TEST METHODOLOGY . 2-1

Contextual Info: PLESSIEY SEMICONDUCTORS Appendix 7 ; CLA60000 SERIES CHANNELLESS CMOS GATE ARRAYS Supersedes December 1988 Edition This advanced family o f gate arrays uses many innovative techniques to achieve 110K gates pa r ch'p - system clock speeds in excess o f 70MHz are achievable. The combinatbn

MT56C0816

Abstract: AW 55 IC LT 5251 80386 cache
Contextual Info: M in P n M * ^ MT56C0816 8K x 16, DUAL 4K x 16 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx 16 SRAM, DUAL 4Kx16 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 16 SRAMs with common addresses and data; also configurable as a single 8K x 16 SRAM

"General Circuit Interface"

Contextual Info: dëà i/W \ National SlA Semiconductor PRELIMINARY TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver General Description The TP3410 is a complete monolithic transceiver for ISDN Basic Access data transmission at either end of the U inter­ face. Fully compatible with ANSI specification T 1.601 -1988,

N20X DIODE

Abstract: A35355 TA8923 ta8872 ta8903 TA8782 ta7833 transistor 123 TA7811 ta8825
Contextual Info: Reliability Update Table of Contents Overview . 1 Organization of the Update . 1

Difference VHC LVC

Abstract: LCX16244 transmission line theory motorola hb205 motorola ac244 AC244 HB205 LVX4245 LVXC3245 VCX16244
Contextual Info: AND8021/D An Introduction to VCX Logic Prepared by: Fred Zlotnick ON Semiconductor http://onsemi.com APPLICATION NOTE ON Semiconductor is introducing a .35 micron family of logic, called VCX. This family achieves a maximum propagation delay of < 3ns and can operate between 3.3 and

micron cmos 1988

Contextual Info: ADVANCE 256K X 18/128K x 36 2.5V I/O, FLOW -THROUGH LATE WRITE SRAM l^ ic n o N Dual Clock and Single Clock FEATURES • Fast cycle times 4.5ns, 5ns, 6ns and 7ns • 256K x 18 or 128K x 36 configurations • Single + 3 .3 V + 0 .3 V /-0 .2 V p o w e r su p p ly (V dd)

SGS-THOMSON SMD

Contextual Info: INTRODUCTION The SGS-THOMSON Microelectronics Group SRAM Databook is a comprehensive collection of information on advanced, high density, high speed SRAM products for specific applications. SGS-THOMSON Microelectronics is a major supplier of a wide range of sem iconductor devices,

burndy 8

Abstract: burndy 10 pin burndy connector IS27C512 IS27HC256 burndy CELP diode databook IS61C1024 IS61C1024L
Contextual Info: ISSI SHORT FORM CATALOG Integrated Silicon Solution, Inc. was founded in 1988 with a new approach to supplying high-speed integrated circuits. Recognizing the multitude of advantages offered by the then new semiconductor foundries, ISSI applied this technology to very high-performance CMOS devices. The

Contextual Info: PERFORMANCE SEMICONDUCTOR G3E D J TObSST? OOOOBM? fl P4C188/P4C188L ULTRA HIGH SPEED 16K x 4 CMOS STATIC RAMS r r-V é -3 3 - /O ' FEBRUARY 1988 - FEATURES • Full CMOS, 6T Cell Single Power Supply — 5V ±10%