MPY112K Search Results

LMU112

Abstract: LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K
Contextual Info: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned

Contextual Info: LMU112 12 x 12-bit Parallel Multiplier D E V I C E S IN C O R P O R A T E D |FEATURES DESCRIPTION The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with TRW's MPY112K.

U112D

Contextual Info: L M U 1 1 2 Features_ Description_ □ 50 ns worst-case multiply time The LMU112 is a high-speed, low power, 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with TRW's MPY112K.

Contextual Info: L O G IC D E V IC E S EbE IN C D • S S b S IG S DG 01231 _ _ 12 x 12-bit Parallel Multiplier FEATURES 5 WÊ r - f ? - LM U 1 1 2 DESCRIPTION □ 50 ns Worst-Case Multiply Time □ Low Power CMOS Technology □ Replaces TRW MPY112K

LMU112

Abstract: LMU112DC50 LMU112DC60 LMU112PC25 LMU112PC50 LMU112PC60 MPY112K
Contextual Info: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ DESCRIPTION 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY112K Two’s Complement or Unsigned

LMU11250

Abstract: LMU112 MPY112K bio39
Contextual Info: LMU112 Features Description □ 50 ns worst-case m ultiply time The LMU112 is a high-speed, low pow er, 12-bit parallel m ultiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible w ith TRW 's MPY112K. □ Low-power CMOS technology

112KJ4C

Abstract: MPY112K 112kj4 trw mpy 16 MPY112 MPY012H MPY112KJ4A MPY112KJ4C TRW LSI Products 112kj
Contextual Info: MPY112K r n Multiplier Features 12x12 Bit, 50ns • 50ns Multiply Time Worst Case The MPY112K is a video-speed 12x12 bit parallel multiplier which operates at a 50ns cycle time (20MHz multiplication rate). The multiplicand and the multiplier may be specified together as two's complement or

LMU112

Abstract: LMU112JC25 LMU112JC50 LMU112PC25 LMU112PC50 MPY112K R13NC 212109
Contextual Info: LMU112 LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier 12 x 12-bit Parallel Multiplier DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned

Contextual Info: LM U112 12 x 12-bit Parallel Multiplier FEATURES □ 25 ns W orst-Case Multiply Time □ Low Power CMOS Technology □ Replaces TRW MPY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Available 100% Screened to MIL-STD-883, Class B

MPY112K

Contextual Info: MPY112K Multiplier 1 2 x 1 2 Bit, 50ns The MPY112K is a video-speed 1 2 x 1 2 bit parallel m ultiplier w h ich operates at a 50ns cycle tim e 20M H z m ultiplication rate . The m ultiplicand and th e m ultiplier may be specified to g e th e r as tw o 's com plem ent or

R238

Contextual Info: ¿oogç LMU112 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D FEATURES □ □ □ □ 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces TRW MPY112K Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Available 100% Screened to

B1016

Abstract: LMU11250
Contextual Info: LMU112 12 x 12-bit Parallel Multiplier □ FV IC E S IN C O R P Q R A T F D FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs □ Package Styles Available:

LMU112

Abstract: 12x12-bit
Contextual Info: LOGIC DEVICES INC TS M ^ S S t S l D S 0 0 0 0 ^ 1 3 T “^ " 07 LMU112 12 x 12-bit parallel multiplier general information The LMU112 is a high-speed, low power, 12-bit parallel multiplier built using advanced CMOS technology.The LMU112 is pin and functionally compatible with

Contextual Info: LMU112 12 x 12-bit Parallel Multiplier D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 25 ns W orst-Case M ultiply Time □ Low Power CMOS Technology □ Replaces Fairchild M PY112K □ Tw o's Complement or Unsigned Operands □ Three-State Outputs