Untitled
Abstract: No abstract text available
Text: MT4C4004J 1 MEG X 4 DRAM M IC R O N DRAM 1 MEG x 4 DRAM FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data Input/Output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory
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MT4C4004J
36bit
225mW
024-cycle
4004JD
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Untitled
Abstract: No abstract text available
Text: MT4C4004J 1 MEG X 4 DRAM [M IC R O N DRAM 1 MEG x 4 DRAM 2 5V, QUAD CAS PARITY, FAST PAGE MODE _ PIN ASSIGNM ENT Top View • Four independent CAS controls, allow ing individual m anipulation to each of the four data in p u t/o u tp u t ports (DQ1 through DQ4).
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MT4C4004J
36-bit
225mW
024-cycle
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Untitled
Abstract: No abstract text available
Text: MICR ON S E M I C O N D U C T O R INC b3E D • b l l l S M T D D D V bb ? 51b ■ MRN MT4C4004J 1 MEG x 4 DRAM I^HCRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST-PAGE-MODE FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual
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MT4C4004J
36bit
275mW
A1993,
T4C4001JDJ
T4C4004JDJ
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Untitled
Abstract: No abstract text available
Text: MT4C4004J 1 MEG X 4 DRAM |U|IC=RON DRAM 1 MEG x 4 DRAM FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data input/output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory
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MT4C4004J
36bit
275mW
024-cycle
24-Pin
MT4C4001JDJ
MT4C4004JDJ
T4C4001JDJ
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T4C4004JDJ
Abstract: marking W7F
Text: MT4C4004J 1 MEG X 4 DRAM I^ IIC R O N DRAM 1 MEG x 4 DRAM FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual manipulation to each of the four data inpu t/output ports (DQ1 through DQ4). • Offers a single chip solution to byte level parity for 36bit words when using 1 M eg x 4 DRAMs for memory
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MT4C4004J
36bit
275mW
024-cycle
24-Pin
MT4C4001JDJ
MT4C4004JDJ
T4C4004JDJ
marking W7F
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Untitled
Abstract: No abstract text available
Text: MICRON M TECHNOLOGY INC SSE D b lllS M R 0QQ433Q MT4C4004J 1 MEG X 4 DRAM IC R O N DRAM 1 MEG x 4 DRAM _ • Four independent CAS controls, allowing individual manipulation to each of the four data Input/Output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory
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0QQ433Q
MT4C4004J
36bit
225mW
024-cycle
00Q4343
T4C4001JDJ
T4C4004JDJ
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Untitled
Abstract: No abstract text available
Text: MT4C4004J 1 MEG X 4 DRAM M IC R O N I TECHNOLOGY. INC. 1 MEG x 4 DRAM DRAM 5V, QUAD CAS PARITY, FAST PAGE MODE _ PIN ASSIG N M EN T Top View • Four independent CAS controls, allowing individual manipulation to each of the four data inpu t/output ports (DQ1 through DQ4).
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MT4C4004J
36-bit
225mW
024-cycle
D015204
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Untitled
Abstract: No abstract text available
Text: MT4C4004J M IC R O N ft 1 MEG X 4 DRAM SÉMCOHJUCTOR 1 MEG x 4 DRAM DRAM QUAD CAS PARITY, FAST PAGE MODE FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data input/output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for
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MT4C4004J
36-bit
275mW
024-cycle
CBR004J
MT4C400AJ
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MT18D236
Abstract: No abstract text available
Text: |U|K=RON 2 MEG DRAM MODULE 2 MEG X MT18D236 36 DRAM MODULE X 36 DRAM FAST-PAGE-MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are TTL-compatible
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MT18D236
72-pin
052mW
024-cycle
72-Pin
DE-12)
MT18D236G-6
CYCLE20
MT18D236
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MT18D236
Abstract: No abstract text available
Text: [MICRON 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG X 36 DRAM FAST-PAGE-MODE FEATURES PIN A SSIG N M EN T Top View • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance CM OS silicon-gate process. • Single 5V ±10% power supply
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MT18D236
72-pin
024-cycle
DE-12)
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Untitled
Abstract: No abstract text available
Text: MICRON S E M I C O N D U C T O R INC b3E J> b l l l S M T OOGfllHS T3fl • MRN m l^ iic n o N 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG x 36 DRAM FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Comm on RA S control per side pinout in a 72-pin
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MT18D236
72-pin
024-cycle
72-Pin
DE-12)
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MT18D236G6
Abstract: No abstract text available
Text: l^ iic n o N 2 MEG X MT18D236 36 DRAM MODULE 2 MEG X 36 DRAM DRAM MODULE FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance, CM OS silicon-gate process. • Single 5V ±10% power supply • All device pins are fully TTL compatible
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MT18D236
72-pin
052mW
024-cycle
18D236M
MT180236
MT18D236G6
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T4C400
Abstract: mt4c4004jdj
Text: M T4C4004J 1 MEG X 4 DRAM l^ldRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST PAGE MODE FEATURES _ • Four independent C A S controls, allo w ing in d ivid u al m anipulation to each of the four data In p u t/O u tp ut ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words w hen using 1 M eg x 4 D R A M s for m emory
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T4C4004J
36bit
225mW
024-cycle
MT4C4001JDJ
MT4C4004JDJ
MT4C4004J
MT4C40040
T4C400
mt4c4004jdj
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Untitled
Abstract: No abstract text available
Text: R /lin S n M I ii^ n w r « MT9D136; W1T18D236 t MEGr 2 MEG x 36 DRAM MODULE 1 MEG, 2 MEG X 36 DRAM MODULE FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin, single-in-line memory module • High-performance CMOS silicon-gate process.
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MT9D136;
W1T18D236
72-pin,
052mW
024-cycle
72-Pin
MT9D136,
MT18D236
36DRAM
T90I36.
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MT18D236
Abstract: No abstract text available
Text: DRAM MODULE 1 MEG, 2 MEG x 36 4, 8 MEGABYTE, 5V 4 ,8ME GABY TE’5VFAST PAGE MODE FEATURES PIN ASSIGNMENT Front View • Common RAS control per side pinout in a 72-pin, single-in-line m emory module (SIMM) • High-performance CM OS silicon-gate process.
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72-pin,
024-cycle
72-Pin
DD-10)
MT9D136,
MT18D236
MT18D236
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MT9D136G-6
Abstract: No abstract text available
Text: |U|IC=RON 1 MEG DRAM MODULE X MT9D136 36 DRAM MODULE 1 MEG x 36 DRAM FAST-PAGE-MODE FEATURES • Common RAS control pinout in a 72-pin single-in-line package • High-performance CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are TTL-compatible
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MT9D136
72-pin
175mW
024-cycle
MT9D136G-6
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Untitled
Abstract: No abstract text available
Text: P IIC R O N 1 MEG DRAM MODULE X MT9D136 36 DRAM MODULE 1 MEG X 36 DRAM FAST PAGE MODE FEATURES PIN ASSIGNMENT Top View OPTIONS 72-Pin SIMM (T-11) MARKING • Timing 60ns access 70ns access 80ns access - 6 - 7 Packages Leadless 72 -pin SIMM Leadless 72-pin SIMM (Gold)
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MT9D136
72-Pin
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Untitled
Abstract: No abstract text available
Text: p ilC R O N 1 MEG X MT9D136 36 DRAM MODULE 1 MEG x 36 DRAM DRAM MODULE FAST PAGE MODE FEATURES PIN ASSIGNMENT Top View OPTIONS 72-Pin SIMM (T -1 1 ) M T9D 136M G ImTiTrn'nTTriïïm iTïïïïiTiriïm „ [rrrrmmiTrrrmmffiTnTnTrrm MARKING • Timing 60ns access
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MT9D136
72-pin
175mW
024-cycle
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MT9D136
Abstract: No abstract text available
Text: |U|IC=RO N 1 MEG DRAM MODULE X MT9D136 36 DRAM M ODULE 1 MEG x 36 DRAM FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Common RAS control pinout in a 72-pin single-in-line package • High-perform ance CM OS silicon-gate process. • Single 5V +10% power supply
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MT9D136
72-pin
024-cycle
DE-11)
T9D136
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