NB4N Search Results

MIL-G-4520C

Abstract: NEMA FR-4 GETEK FR4 lamination TTL johnson ring counter 4520C HC49US27 160-1183-1-ND CDRH74102MC C0603C103K5RACT 000000M
Contextual Info: NB4N441MNGEVB NB4N441MNGEVB Evaluation Board User's Manual Device Name: NB4N441MN http://onsemi.com EVAL BOARD USER’S MANUAL Description Board Features The NB4N441MNG is a precision clock PLL based synthesizer which generates select differential LVPECL clock output frequencies from 12.5 MHz to 425 MHz. A

Contextual Info: NB4N840M 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM Description The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for

Contextual Info: NB4N507ADEVB NB4N507ADEVB Evaluation Board User's Manual http://onsemi.com Description EVAL BOARD USER’S MANUAL The NB4N507ADEVB Evaluation Board provides a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of the

Contextual Info: NB4N840MMNEVB Evaluation Board User's Manual for NB4N840M http://onsemi.com EVAL BOARD USER’S MANUAL Description applications. Each 2 x 2 crosspoint switch can fan−out and/or multiplex up to 3.2 Gb/s data and 2.7 GHz clock signals. Internally terminated differential CML inputs accept

Contextual Info: NB4N855SMEVB Evaluation Board User's Manual for NB4N855S http://onsemi.com EVAL BOARD USER’S MANUAL Description Board Lay−Up ON Semiconductor has developed an evaluation board for the NB4N855S device as a convenience for the customers interested in performing their own device engineering

NB4N441MNG

Abstract: NB4N441MNR2G NB4N441 0b161
Contextual Info: NB4N441 3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Differential LVPECL Output http://onsemi.com Description The NB4N441 is a precision clock synthesizer which generates a differential LVPECL clock output frequency from 12.5 MHz to 425 MHz. A Serial Peripheral Interface SPI is used to configure the

NB4N111KMNG

Abstract: NB4N111KMNR4G QFN32 488AM
Contextual Info: NB4N111K 3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output http://onsemi.com Description The NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultra low propagation delay variation. The NB4N111K is designed with HCSL clock distribution for FBDIMM

ps2018

Contextual Info: NB4N840M 3.3V 2.7Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM Description The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for

AN1642

Abstract: NB4N507A NB4N507AD NB4N507ADG NB4N507ADR2 NB4N507ADR2G transistor marking 12x
Contextual Info: NB4N507A 3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer Description The NB4N507A is a precision clock synthesizer which generates a very low jitter differential PECL output clock. It produces a clock output based on an integer multiple of an input reference frequency.

Contextual Info: NB4N11S 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator The NB4N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

Contextual Info: NB4N316M 3.3 V AnyLevel] Receiver to CML Driver/Translator with Input Hysteresis 2.0 GHz Clock / 2.5 Gb/s Data http://onsemi.com The NB4N316M is a differential Clock or Data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating up to

NB4N441

Abstract: NB4N441MNG NB4N441MNR2G NB4N
Contextual Info: NB4N441 3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Differential LVPECL Output http://onsemi.com Description The NB4N441 is a precision clock synthesizer which generates a differential LVPECL clock output frequency from 12.5 MHz to 425 MHz. A Serial Peripheral Interface SPI is used to configure the

QFN-24 footprint

Abstract: NB4N441 NB4N441MNG NB4N441MNR2G
Contextual Info: NB4N441 3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Differential LVPECL Output http://onsemi.com Description The NB4N441 is a precision clock synthesizer which generates a differential LVPECL clock output frequency from 12.5 MHz to 425 MHz. A Serial Peripheral Interface SPI is used to configure the

32K243-40ME3

Abstract: RO6002 06035C103KAT2A 32K243 NB4N527S T491C106K016AS Rosenberger 32K243-40ME3 pcb design lab manual
Contextual Info: NB4N527SMNEVB Evaluation Board Manual for NB4N527S http://onsemi.com EVALUATION BOARD MANUAL Board Lay−Up INTRODUCTION The 16−lead QFN evaluation board is implemented in four layers with split dual power supplies (Figure 2, Evaluation Board Lay−up). For standard lab setup, a split

NB4N316M

Abstract: NB4N316MDTG
Contextual Info: NB4N316M 3.3 V AnyLevel] Receiver to CML Driver/Translator with Input Hysteresis 2.0 GHz Clock / 2.5 Gb/s Data http://onsemi.com The NB4N316M is a differential Clock or Data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating up to

Contextual Info: NB4N527S 3.3V, 2.5Gb/s Dual AnyLevel to LVDS Receiver/Driver/Buffer/ Translator with Internal Input Termination http://onsemi.com NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal LVPECL, CML,

7132G

Abstract: TSSOP-28 Package Dimensions. TSSOP-28. 14 1. 15 28. E. H NB4N
Contextual Info: NB4N7132 Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA Up to 1.5 Gb/s http://onsemi.com Description The NB4N7132 is a high performance 3.3 V Serial Link Replicator which provides the function of serial loop replication and serial loopback control commonly required in Fibre Channel, GbE, HDTV

Contextual Info: Enabling Energy Efficient Solutions Product Overview Created on: 10/26/2011 NB4N507A: 3.3 V / 5.0 V, 50 to 200 MHz PECL Clock Synthesizer For complete documentation, see the data sheet Product Description The NB4N507A is a precision clock synthesizer which generates a very low jitter differential PECL output clock. It produces a

HC-SL

Contextual Info: Enabling Energy Efficient Solutions Product Overview Created on: 10/26/2011 NB4N121K: 1:21 Differential Clock/Data Fanouot Buffer with HCSL Output For complete documentation, see the data sheet Product Description The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low

Contextual Info: NB4N855S 3.3 V, 1.5 Gb/s Dual AnyLevel to LVDS Receiver/Driver/Buffer/ Translator Description NB4N855S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevel input signal LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS to LVDS. Depending on the distance,

NB4N507AG

Abstract: NB4N507ADG NB4N507ADR2 NB4N507A NB4N507AD transistor marking 12x
Contextual Info: NB4N507A 3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer Description The NB4N507A is a precision clock synthesizer which generates a very low jitter differential PECL output clock. It produces a clock output based on an integer multiple of an input reference frequency.

485G

Abstract: NB4N527S NB4N527SMN NB4N527SMNG OC48
Contextual Info: NB4N527S 3.3V, 2.5Gb/s Dual AnyLevel to LVDS Receiver/Driver/Buffer/ Translator with Internal Input Termination http://onsemi.com NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal LVPECL, CML,

NB4N316M

Abstract: NB4N316MDTG
Contextual Info: NB4N316M 3.3 V AnyLevelt Receiver to CML Driver/Translator with Input Hysteresis 2.0 GHz Clock / 2.5 Gb/s Data http://onsemi.com The NB4N316M is a differential Clock or Data receiver and will accept AnyLevelt input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating

Contextual Info: NB4N527SMNEVB Evaluation Board Manual for NB4N527S http://onsemi.com EVALUATION BOARD MANUAL INTRODUCTION Board Lay−Up The 16−lead QFN evaluation board is implemented in four layers with split dual power supplies (Figure 2, Evaluation Board Lay−up). For standard lab setup, a split