NC7SV58P6X Search Results
NC7SV58P6X Datasheets (2)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
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NC7SV58P6X |
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TinyLogic ULP-A Universal Configurable 2-Input Logic Gates | Original | 197.58KB | 11 | ||
NC7SV58P6X |
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TinyLogic ULP-A Universal Configurable 2-Input Logic Gates; Package: SC70; No of Pins: 6; Container: Tape & Reel | Original | 634.09KB | 14 |
NC7SV58P6X Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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NC7SV57
Abstract: NC7SV57L6X NC7SV57P6X NC7SV58 NC7SV58L6X NC7SV58P6X
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NC7SV57 NC7SV58 NC7SV57 NC7SV58 NC7SV57L6X NC7SV57P6X NC7SV58L6X NC7SV58P6X | |
AEC-Q100-006
Abstract: aec-q100 001 NC7SP125P5X b0332 NC7SV86P5X aec-q100 JESD22-A110 0.35 tsmc cmos front of fabrication process NC7WV04P6X
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Q20030061 FS35C SC-70 NC7SP00P5X NC7SP05P5X NC7SP126P5X NC7SP158P6X NC7SP32P5X NC7SP57P6X NC7SPU04P5X AEC-Q100-006 aec-q100 001 NC7SP125P5X b0332 NC7SV86P5X aec-q100 JESD22-A110 0.35 tsmc cmos front of fabrication process NC7WV04P6X | |
NC7SV57
Abstract: NC7SV57L6X NC7SV57P6X NC7SV58 NC7SV58L6X NC7SV58P6X
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NC7SV57 NC7SV58 NC7SV57 NC7SV58 NC7SV57L6X NC7SV57P6X NC7SV58L6X NC7SV58P6X | |
NC7SV57Contextual Info: NC7SV57 / NC7SV58 TinyLogic ULP-A Universal Configurable Two-Input Logic Gates Features Description ̇ ̇ 0.9V to 3.6V VCC Supply Operation ̇ Extremely High Speed tPD - 2.5ns: Typical for 2.7V to 3.6V VCC - 3.1ns: Typical for 2.3V to 2.7V VCC - 4.0ns: Typical for 1.65V to 1.95V VCC |
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NC7SV57 NC7SV58 NC7SV58 NC7SV57 NC7V58 | |
NC7SV57
Abstract: NC7SV57P6X NC7SV58 NC7SV58L6X NC7SV58P6X NC7SV57L6X 2-input XOR using 4 2-input NAND gates mark v58 NC7SV57P6
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NC7SV57 NC7SV58 NC7SV57 NC7SV58 NC7SV57P6X NC7SV58L6X NC7SV58P6X NC7SV57L6X 2-input XOR using 4 2-input NAND gates mark v58 NC7SV57P6 | |
NC7SV57Contextual Info: Revised September 2002 NC7SV57 • NC7SV58 TinyLogic ULP-A Universal Configurable 2-Input Logic Gates General Description Features The NC7SV57 and NC7SV58 are universal configurable 2-input logic gates from Fairchild’s Ultra Low Power ULP-A Series of TinyLogic. ULP-A is ideal for applications |
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NC7SV57 NC7SV58 NC7SV57 | |
NC7SV57
Abstract: CMOS XNOR Gates NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58 NC7SV58FHX NC7SV58L6X NC7SV58P6X TinyLogic h4
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NC7SV57 NC7SV58 NC7SV58 NC7SV57 NC7V58 CMOS XNOR Gates NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58FHX NC7SV58L6X NC7SV58P6X TinyLogic h4 | |
pin configuration of logic gates
Abstract: NC7SV57 NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58 NC7SV58FHX NC7SV58L6X NC7SV58P6X logic gates pin configuration
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NC7SV57 NC7SV58 NC7SV58 NC7SV57 NC7V58 pin configuration of logic gates NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58FHX NC7SV58L6X NC7SV58P6X logic gates pin configuration | |
logic gates pin configuration
Abstract: pin configuration of logic gates 2-input-XNOR using nand and not NC7SV58FHX NC7SV57 NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58 NC7SV58L6X
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NC7SV57 NC7SV58 NC7SV58 NC7SV57 NC7V58 logic gates pin configuration pin configuration of logic gates 2-input-XNOR using nand and not NC7SV58FHX NC7SV57FHX NC7SV57L6X NC7SV57P6X NC7SV58L6X | |
AEC-Q100-006
Abstract: aec-q100 001 AEC-Q100 NC7SP125P5X NC7SV86P5X JESD22-A110 NC7SV158 tsmc cmos NC7SV125P5X JESD22 a113
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Q20030060 FS35C SC-70 NC7SP00P5X NC7SP05P5X NC7SP126P5X NC7SP158P6X NC7SP32P5X NC7SP57P6X NC7SPU04P5X AEC-Q100-006 aec-q100 001 AEC-Q100 NC7SP125P5X NC7SV86P5X JESD22-A110 NC7SV158 tsmc cmos NC7SV125P5X JESD22 a113 |