P181 IC Search Results

P181

Abstract: P181 G P180 MW187 tr5vdc
Contextual Info: /1 6 4.8mm »SNÄPHIN PANEL MOUNT LEDs COLOR CODE LEGEND PART NUMBER SELECTION GUIDE r LENS CHARACTERISTICS CODE (SEE LEGEND SINGLE CHIP P181 P187 LED COLOR CHARACTERISTICS ELECTRICAL CHARACTERISTICS COLOR CODE TR5 TY5 TG5 LENS CHARACTERISTICS OPTIONS T-W IR E TERMINAL

p181 4 pin

Abstract: 511000 dram S511000 TC 511000
Contextual Info: MOSEL_MS511000 may isso 1,048,576 x 1 Fast Page Mode CMOS Dynamic RAM FEATURES GENERAL DESCRIPTION • Available in 70/80/100/120 ns The M O SEL M S511000 is a CM OS dynam ic RAM organized as 1,048,576 w ords x 1 bit. The M S511000 has been designed for m ainfram e, buffer memory,

P331

Abstract: p181 P086 p323 P085 P237 p044 p055 P084 P005
Contextual Info: 5 6 7 GND UVCC3 GND VCC3C GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VSS5 MD_2 MD_1 X0 X1 VSS5 X1A X0A MD_0 P16_1/PPG9 P16_0/PPG8 P20_6/SCK3/FRCK3 P20_5/SOT3 P20_4/SIN3 P20_2/SCK2/FRCK2 P20_1/SOT2 P20_0/SIN2 P24_7/INT7

Contextual Info: MOSEL M S511000 1,048,576 x 1 Fast Page Mode CMOS Dynamic RAM F E A TU R ES G E N E R A L D E S C R IP TIO N • Available in 70/80/100/120 ns The MOSEL MS511000 is a CMOS dynamic RAM organized as 1,048,576 words x 1 bit. The MS511000 has been designed for mainframe, buffer memory,

p181 4 pin

Abstract: MS511000-12PC p181 MS511000-10 MS511000-12 MS511000-70 MS511000-80 S511000-70 S5110 S511000
Contextual Info: M OSEL M S511000 1,048,576 x 1 Fast Page Mode CMOS Dynamic RAM FEATURES G E N E R A L D E S C R IP T IO N • Available in 70/80/100/120 ns The M O SEL M S 511000 is a CM O S dynam ic RAM organized as 1,048,576 words x 1 bit. The M S 511000 has been designed for m ainfram e, buffer memory,

P181 G

Abstract: DRAM 511000-70 ss1891 p181 4 pin 511000-70
Contextual Info: MOSEL M S511000 1,048,576 x 1 Fast Page Mode CMOS Dynamic RAM FEATURES GENERAL DESCRIPTION • Available in 70/80/100/120 ns The MOSEL MS511000 is a CMOS dynamic RAM organized as 1,048,576 words x 1 bit. The MS511000 has been designed for mainframe, buffer memory,

IDT72401

Abstract: IDT72402 IDT72403 IDT72404
Contextual Info: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • • • • • • First-ln/First-Out Dual-Port memory 64 x 4 organization IDT72401/72403

Contextual Info: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 IDT72404 are asynchronous high-performance First-ln/First-Out memories organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an Output Enable OE pin. The FlFOs accept 4-bit or 5-bit data at the data input

IDT72401

Abstract: IDT72402 IDT72403 IDT72404 300 mil, D18-1 IDT
Contextual Info: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • • • • • • • First-ln/First-Out Dual-Port memory 64 x 4 organization IDT72401/72403

Contextual Info: IDT72401 IDT72402 IDT72403 IDT72404 CMOS PARALLEL FIFO 64 x 4 and 64 x 5 IDT72404 are asynchronous high-performance First-ln/First-Out memories organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an Output Enable OE pin. The FlFOs accept 4-bit or 5-bit data at the data input

MOSFET P239

Abstract: XC4000XLA VDR P275 L20 P55 MOSFET XC4000E XC4000X XC4000XL XC4000XV XC4013XLA XC4028XLA
Contextual Info: XC4000XLA/XV Field Programmable Gate Arrays R February 1, 1999 Version 1.0 6* Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the

J29 P190

Abstract: p331 TRANSISTOR p477 p525 P364 P521 G P440 C 05 P521 G2 p372 transistor P519
Contextual Info: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

P521 FAIRCHILD

Abstract: J29 P190 P211A11 fairchild AG12 diode fairchild Ah7 FAIRCHILD AB29 transistor P421 fairchild AJ23 P449 P315 transistor
Contextual Info: MSX Family Datasheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

Contextual Info: CMOS PARALLEL FIFO 64 x 4 and 64 x 5 FEATURES: • • • • • • • • • • • • • • • • • First-In/First-Out Dual-Port memory 64 x 4 organization IDT72401/72403 64 x 5 organization (IDT72402/72404) RAM-based FIFO with low fall-through time

Contextual Info: CMOS PARALLEL FIFO 64 x 4 and 64 x 5 | dt Integrated D evize Technology, Inc. FEATURES: • • • • • • • • • • • • • • • • • First-In/First-Out D ual-Port mem ory 64 x 4 organization ID T72401/72403) 64 x 5 organization (ID T72402/72404)

P132-P134

Abstract: p331 TRANSISTOR P452
Contextual Info: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

aw7 TRANSISTOR

Abstract: P449 I-CUBE iq P-033 Bus repeater p426 P-238 P122-P120 p331 TRANSISTOR P339
Contextual Info: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

11AK12

Abstract: 4062XLA Trans Metrics P100 4044XL AD 690 xilinx HQ240 diode ak14
Contextual Info: £ X IU N X XC4000XLA/XV Field Programmable Gate Arrays February 1, 1999 Version 1.0 Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC 4000XLA devices are improved versions of X C 4000X L devices. The XC4000X V devices have the

xc4005 pg156

Abstract: P181 Japan X6569 X5326 708 p113 XC4013 PG223 XC4005PG156 metal film resistors n4 150C 3b365 k1168
Contextual Info: XC4000 High-Reliability Logic Cell Array Family  March 1997 version 1.0 Product Description Features Description • Available in Class B fully compliant and military temperature range only versions – MIL-STD-883 Class B processing complies with paragraph 1.2.1

transistor P397

Abstract: P521 G P089 P521 FAIRCHILD transistor P479 MSX532 MSX532TB792 P039 UP501 P449
Contextual Info: Revised June 2002 MSX532 532 Port Digital Crosspoint Switch with LVTTL I/O’s General Description Features The MSX family of SRAM-based bit-oriented switching devices offer flow-through NRZ data rates of up to 150Mb/s and registered clock frequencies of up to 75MHz. The I/O

diagram of ic p181

Abstract: P181 BL 712 P181 050 P181
Contextual Info: CMOS PARALLEL FIFO 64 x 4 and 64 x 5 FEATURES: • • • • • • • • • • • • • • • • • First-In/First-Out Dual-Port memory 64 x 4 organization IDT72401/72403 64 x 5 organization (IDT72402/72404) RAM-based FIFO with low fall-through time

ptc j29 p190

Abstract: elex 15101 datasheet str 5707 intel 865 MOTHERBOARD pcb CIRCUIT diagram str 5707 pci pcb layout vhdl code for 8-bit parity generator XCS40PQ208 machine maintenance checklist CD 5888
Contextual Info: Xilinx PCI the CORE of a GREAT IDEA The Programmable Logic CompanySM Printed in U.S.A. Data Book 2100 Logic Drive San Jose, CA 95124-3400 Tel: 1-408-559-7778 Fax: 1-408-559-7114 e-mail: hotline@xilinx.com web: www.xilinx.com PN 0401764 5/98 Xilinx PCI The

dt72401

Contextual Info: C M O S P A R A L L E L FI FO 64 x 4 and 64 x 5 FEATURES: • • • • • • • • • • F irst-In /F irst-O u t D u a l-P o rt m e m o ry 6 4 x 4 o rg a n iza tio n ID T 7 2 4 0 1/72403 6 4 x 5 o rg a n iza tio n (ID T 7 2 4 0 2 /7 2 4 0 4 ) R A M -b a s e d F IF O w ith lo w ta il-th ro u g h tim e

transistor P397

Abstract: transistor P479 P449 p331 TRANSISTOR transistor k38 v6 transistor P519 am2 am3 p055 power transistor f AJ38 w38 transistor
Contextual Info: MSX532 Matrix Switch Preliminary Data Sheet Features Description • • The MSX family of SRAM-based bit-oriented switching devices offers flow-through NRZ datarates of 300Mbps and registered clock frequencies of 200MHz. The 532 I/O Buffers IOBs are individually configured. The IOBs can be connected