P345 Search Results

AV02-3698EN

Abstract: so6 package
Contextual Info: ACPL-P345 and ACPL-W345 1.0 Amp Output Current Power & SiC MOSFET Gate Drive Optocoupler with Rail-to-Rail Output Voltage in Stretched SO6 Data Sheet Description Features The ACPL-P345/W345 contains an AlGaAs LED, which is optically coupled to an integrated circuit with a power

P3459

Abstract: A2LB
Contextual Info: HAMAMATSU CORP ITE D • HSETbCH HAMAMATSU DOGSbflT Ô ■ PHOTOINTERRUPTER P3459 TECHNICAL DATA C Phototransistor output, Ultra-compact package 4.5 x 4.0 x 4.1mm The P3459 is a photointerrupter which uses a high-power in­ frared LED on the light-emitting side and a high-sensitivity

P420L

Abstract: P344L COP420L COP445L E3VU P345L P34XL Diode p420l
Contextual Info: COP444L/COP445L/COP344L/P345L National A M Sem iconducto r COP444L/COP445L/COP344L/P345L Single-Chip N-Channei Microcontrollers General Description Features The CO P444L, CO P445L, CO P344L, and CO P345L SingleChip N-Channel Microcontrollers are members of the

Contextual Info: ACPL-P345 and ACPL-W345 1.0 Amp Output Current Power & SiC MOSFET Gate Drive Optocoupler with Rail-to-Rail Output Voltage in Stretched SO6 Data Sheet Description Features The ACPL-P345/W345 contains an AlGaAs LED, which is optically coupled to an integrated circuit with a power

P345

Contextual Info: Schem atic: r- ' H .j E le c tric a l Specifications: @25°C Iso la tio n V o lta g e : 1 5 0 0 V rm s In p u t to Iso la tio n V o lta g e : 5 0 0 V rm s ( P 1 + 4 + 2 Turns R atio: RX 1 CT: 1 ± 3 % O u tp u t to P345+5) TX 1CT:1.41CT ± 3 % OCL P 1 - Z :

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD P34563 Preliminary LINEAR INTEGRATED CIRCUIT PWM CONTROL 3A STEP-DOWN CONVERTER  DESCRIPTION The UTC P34563 consists of step-down switching regulator with PWM control. The UTC P34563 provides low-ripple power, high efficiency,

Contextual Info: 74ACT11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS129 - P3450, MARCH 1990-R EVISED APRIL 1993 * Inputs Are TTL-Voltage Compatible DB, DW OR NT PACKAGE TOP VIEW * Contains Eight D-Type Flip-Flops 1Q [ * Clock Enable Latched to Avoid False Clocking ] C LKEN

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD P34563 Preliminary LINEAR INTEGRATED CIRCUIT PWM CONTROL 3A STEP-DOWN CONVERTER  DESCRIPTION The UTC P34563 consists of step-down switching regulator with PWM control. The UTC P34563 provides low-ripple power, high efficiency,

Contextual Info: M ODEL: BU-P3452 Shorting B ar Pin Tip Plug .25” 6.35m m \Shorting//''\\'\ Bar vriy .28 (7.11mm) - .06” (1,52mm) ACCEPTS .080” (2.03m m ) PIN TIP. .63” (1 6.0mm) V N ,080 ( 2. 03 ) V V Q-Q D \!/ \J SCHEMATIC MATERIALS: B o d y -A B S (Black)

P281 B01

Abstract: G187
Contextual Info: LogiCORE IP Processing System 7 v4.02a DS871 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Processing System 7 IP is the software interface around the Zynq Processing System. The Zynq -7000 family consists of an system-on-chip (SoC) style

8 bit full adder

Abstract: LD78 CDUD4 CBU12 266 XnOR GATE BI48 CBD12 FD51 mux24 MUX82
Contextual Info: ispLSI Macro Library Reference Manual Version 8.2 Technical Support Line: 1-800-LATTICE or 408 826-6002 IDE-ISPML-RM 8.2.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without

Contextual Info: User’s Manual The sales of these products are limited for China, Hong Kong, and India. R7F0C008A/B/F, R7F0C009A/B/F 16 User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications,

P3458

Contextual Info: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ SCAS11 5 - D3458, MARCH 1990-R EV IS ED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Independent Registers A and B Buses Multiplexed Real-Time and Stored Data

7486 XOR GATE

Abstract: circuit diagram of half adder using IC 7486 7486 2-input xor gate ic 7486 XOR GATE pin configuration IC 7486 pin configuration of 7486 IC vhdl code for vending machine pin DIAGRAM OF IC 7486 data sheet IC 7408 laf 0001
Contextual Info: Lattice Semiconductor Handbook 1994 Click on one of the following choices: • Table of Contents • How to Use This Handbook • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Handbook 1994 i Copyright © 1994 Lattice Semiconductor Corporation.

A2L6

Abstract: A3L12 a2l1 A3L10 CCD595 Contact image sensor fairchild P115 FAIRCHILD A3R16 P210 fairchild A1R8
Contextual Info: PRELIMINARY DATA SHEET CCD595 9216 x 9216 Pixel Image Area Full Frame CCD Image Sensor FEATURES • 9216 x 9216 Full Frame CCD Array • 8.75 µm x 8.75 µm Pixels • 80.64mm x 80.64mm Image Area • 100% Fill Factor • Non Multi-Pinned Phase MPP Operation

8 bit adder and subtractor

Abstract: full subtractor 4 bit binary full adder and subtractor 8 bit adder p345 8 bit carry adder ADDER
Contextual Info: Adder and Subtractor Macros Using Lattice Design Tools c4 = g3 + p3 . c3 = g3 + p3 g2 + p2 . g1 + p2 . p1 . g0 + p2. p1 . p0 . c0 Carry-Lookahead Adders Arithmetic logic blocks, such as adders and subtractors, are increasingly becoming performance bottlenecks in

C6198

Abstract: a17 c178 100v 12p quanta TMS 3617 CX20468-31 mtp42 cpu c644 100v 27p capacitor 100u 63V a70 4013 100 12p Quanta KT2
Contextual Info: 5 4 3 2 PCB Rev: A 1 Sch ver : 20040402_07 KT2 BLOCK DIAGRAM D PCB STACK UP LAYER 1 : TOP D PENTIUM-M / Montara-GM / ICH4-M LAYER 2 : GND LAYER 3 : IN1 CPU PENTIUM-M CPU THERMAL SENSOR LAYER 4 : IN2 GMT-781 478 Pins micro FC-PGA PAGE: 3 LAYER 5 : VCC 14.318MHz

wireless TV headphone mini project

Abstract: quanta hp pavilion g6 LED1013 PIC PROJECT CCS C TOUCHPAD PC97551 MC1231 p31b diode quanta computer C3452
Contextual Info: 1 2 3 4 5 6 8 CT1 BLOCK DIAGRAM PCB STACK UP LAYER 1 : TOP PENTIUM-M / Montara-GM / ICH4-M LAYER 2 : GND A 7 LAYER 3 : IN1 CPU PENTIUM-M CPU THERMAL SENSOR LAYER 4 : IN2 GMT-781 478 Pins micro FC-PGA PAGE: 3 LAYER 5 : VCC 14.318MHz A SYSTEM POWER(1.2V/1.05V/1.25V)

Quanta CT3 block diagram

Abstract: C933 ICS954206A capacitor 14K 510 IC HS 8110 31CT3MB0031 HP Pavilion g6 s m r707 ak3 Quanta CT3 quanta
Contextual Info: 1 2 3 4 5 6 8 CT3 BLOCK DIAGRAM PCB STACK UP LAYER 1 : TOP LAYER 2 : GND A LAYER 4 : IN2 MAX6657 / GMT-781 PAGE: 3 +3V LAYER 5 : VCC LAYER 6 : BOT PENTIUM-M / ALVISO / ICH6-M Processor Intel Pentium-M Intel Celeron-M CPU THERMAL SENSOR LAYER 3 : IN1 V CC_CORE

1Bt 87

Abstract: P3420 p32100 P3412 polytron p35 P53-15L P38-12S 1BT 88 P3475 POLYTRON P33-48ST
Contextual Info: P POLYTRON DEVICES, Inc. LINEAR ENCAPSULATED POWER MODULES REGULATED 5Vdc-250Vdc P.C. CARD OR CHASSIS MOUNTING Specifications FEATURES • UL, CE & CSA Approved All Models • Regulation Line & Load 0.2% to 0.02% • P.C. Card/Chassis Mounting 115 Vac, 50 to 400 Hz @ 25°C

P132-P134

Abstract: p331 TRANSISTOR P452
Contextual Info: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

aw7 TRANSISTOR

Abstract: P449 I-CUBE iq P-033 Bus repeater p426 P-238 P122-P120 p331 TRANSISTOR P339
Contextual Info: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

74AC11648

Abstract: CBAF
Contextual Info: 54AC11648, 74AC11648 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS _ D3457, M AR C H 1990 -R E V IS E D M AY 1990 Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data 54AC11648 . . . JT PACKAGE

ic A2611

Abstract: a2611 A2631 a2610 a2633 s2s65a00 A2624 18vdc power supply Epson EPD controller A2651
Contextual Info: S2S65A00 Technical Manual Rev.1.2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material