PAL 16 MACROCELLS Search Results

jw32

Contextual Info: CYPRESS PRELIMINARY Flash Erasable, Reprogrammable CMOS PAL Device Features Up to 16 input terms and 8 outputs • Advanced second-generation PAL ar­ chitecture • Low power — 90 mA max. commercial 10,15, 25 ns — 115 mA max. commercial (7 ns) — 130 mA max. military/industrial

Contextual Info: PRELIMINARY W f C Y PR ESS Flash Erasable, Reprogrammable CMOS PAL Device Features Up to 16 input terms and 8 outputs • Advanced second-generation PAL ar­ chitecture DIP, LCC, and PLCC available • Low power — 90 mA max. commercial 10,15, 25 ns — 115 mA max. commercial (7 ns)

Contextual Info: COM’L: -2 5 IND: -2 5 n PALCE22V1OZ-25 Zero-Power 24-Pin EE CMOS Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Zero-power CMOS technology ■ - Varied product term distribution allows up to 16 product terms per output for complex functions

palce16v8 programming guide

Abstract: PALCE16V8 16V8-10 CERAMIC LEADLESS CHIP CARRIER PALCE16V8-10 PALCE16V8-15 PALCE16V8-25 PALCE16V8-5 PALCE16V8-7 PALCE16V8L-15
Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS PALCE16V8 Flash-Erasable Reprogrammable CMOS PAL Device Features • Up to 16 input terms and eight outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • Active pull-up on data input pins

16v8-25

Abstract: 16V8-10 palce16v8 programming guide 16V8-15 Cypress 16V8-15 16V85 PALCE16V8-5 PALCE16V8-7 PALCE16V8L-25 ULTRA37000
Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS PALCE16V8 Flash-Erasable Reprogrammable CMOS PAL Device Features • Up to 16 input terms and eight outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • Active pull-up on data input pins

16v8

Abstract: 16v8 programming 16v8 spec palce16v8 programming guide PALCE16V8 PALCE16V8-10 PALCE16V8-15 PALCE16V8-25 PALCE16V8-5 PALCE16V8-7
Contextual Info: 16V8 PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL Device Features • Up to 16 input terms and 8 outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • 10 ns military/industrial versions 7 ns tCO 10 ns tS 10 ns tPD

16V83

Abstract: CE16V8 16V88 palce16v8 programming guide 16V8 PALCE16V8 PALCE16V8-10 PALCE16V8-15 PALCE16V8-25 PALCE16V8-5
Contextual Info: fax id: 6009 1P AL CE 16 V8 PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL Device Features • QSOP packaging available — 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • Active pull-up on data input pins • Low power version 16V8L

16V88

Abstract: 16V8 PALCE16V8 PALCE16V8-10 PALCE16V8-15 PALCE16V8-25 PALCE16V8-5 PALCE16V8-7 PALCE16V8L-15 PALCE16V8L-25
Contextual Info: PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL Device • Up to 16 input terms and 8 outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • 10 ns military/industrial versions 7 ns tCO 10 ns tS 10 ns tPD 62-MHz state machine

16v8

Abstract: 16R4 programming specification 64 CERAMIC LEADLESS CHIP CARRIER LCC application PAL 16l8 16v8 programming 16V8-10 CERAMIC LEADLESS CHIP CARRIER palce16v8 programming guide PALCE16V8-15DMB PALCE16V8-25PC
Contextual Info: 8 PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL Device • Up to 16 input terms and 8 outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • 10 ns military/industrial versions 7 ns tCO 10 ns tS 10 ns tPD 62-MHz state machine

palce16V8 programming

Abstract: palce16v8 programming guide palce16v
Contextual Info: PALCE16V8 Flash-Erasable Reprogrammable CMOS PAL Device Features • Up to 16 input terms and eight outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • Active pull-up on data input pins • Low power version 16V8L — 55 mA max. commercial (10, 15, 25 ns)

16v8

Abstract: 16V8-5 16v8 programming PALCE16V8-15 rjoc 16V8L SLD15 16v8 programming Guide ATH 2053 PALCE16V8-10
Contextual Info: PA LCE16V8 7CYPRESS Flash Erasable, Reprogrammable CMOS PAL Device • Up to 16 input term s and 8 outputs Features • 7.5 ns com ’l version 5 ns tco 5 ns ts 7.5 ns t PD 125-M Hz state m achine • Active pull-up on data input pins • Low power version 16V8L

im4A

Abstract: PAL PATTERN GENERATOR ispMACH 4A Family SIGNAL PATH designer transistor m4a
Contextual Info: ispMACH 4A Family Architectural Description TM The macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells internally in a PAL block Table 1 . ispMACH4A Family Introduction The fundamental architecture of ispMACH 4A devices

MACH355

Abstract: HP3070 MACH111SP
Contextual Info: MACH 4 FAMILY 1 FINAL COM’L: -15 IND: -20 MACH4-96/96-15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 144 Pins in PQFP ◆ 96 Macrocells ◆ ◆ ◆ ◆ ◆ MACH 4 Family ◆ 15 ns tPD Commercial, 20 ns tPD Industrial ◆ 47.6 MHz fCNT

micro flex teradyne jtag

Abstract: MACH355 HI-LO ALL-07 542-0388 teradyne flex tester teradyne lasar HP3070 MACH111SP gate and pal architect
Contextual Info: MACH 4 FAMILY 1 FINAL COM’L: -15 IND: -18 Lattice Semiconductor MACH4-96/96-15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 144 Pins in PQFP ◆ 96 Macrocells ◆ ◆ ◆ ◆ ◆ MACH 4 Family ◆ 15 ns tPD Commercial, 18 ns tPD Industrial

Contextual Info: FINAL COM’L: -12.Q-20 Advanced Micro Devices MACH435-12, Q-20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins in PLCC ■ Up to 20 product terms per function, with XOR ■ 128 Macrocells ■ Flexible clocking ■ 12nstpD — Four global clock pins with selectable edges

MACH111SP

Abstract: MACH465 MACH4-256 mach4256
Contextual Info: MACH 4 FAMILY 1 FINAL COM’L: -10/12/15 IND:-12/14/18 MACH4-256/MACH4LV-256 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 208 pins in PQFP 256 macrocells 10 ns tPD Commercial, 12 ns tPD Industrial

MACH111SP

Contextual Info: 1 PRELIMINARY MACH 4 FAMILY COM’L: -7/10/12/15 IND: -10/12/14/18 MACH4-128N/MACH4LV-128N High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 84-pins in PLCC 128 macrocells 7.5 ns tPD Commercial, 10 ns tPD Industrial

palasm

Abstract: ADVANCED MICRO DEVICES PAL22V10 application of programmable array logic
Contextual Info: A d v a n c e I n fo r m a t io n COM’L PALCE22V10Z-25 Advanced Micro Devices Zero Standby Power 24-pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • Zero standby power allows battery operation ■ 10 macrocells programmable as registered or

Contextual Info: FINAL COM’L: -12/15/20 IND: 14/18/24 a MACH110-12/15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 38 Inputs ■ 32 Macrocells ■ 32 Outputs ■ 12 n s t P D Commercial 14 nstpD Industrial

PAL22V16

Abstract: MACH110 MACH210 MACH215 PAL22V10 AIR33
Contextual Info: FINAL COM’L: -12/15/20 IND: -14/18/24 MACH110-12/15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Outputs ■ 32 Macrocells ■ 32 Flip-flops; 2 clock choices ■ 12 ns tPD Commercial 14 ns tPD Industrial

Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH230-15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 70 Inputs ■ 128 Macrocells ■ 64 Outputs ■ 15 ns tpD Commercial 18 ns tpD Industrial ■ 128 Flip-flops; 4 clock choices

MACH4-128

Abstract: MACH446 MACH111SP MACH445 teradyne tester test system O16I
Contextual Info: 1 PRELIMINARY MACH 4 FAMILY COM’L: -7/10/12/15 IND: -10/12/14/18 MACH4-128/MACH4LV-128 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 100 pins in PQFP and TQFP 128 macrocells 7.5 ns tPD Commercial, 10 ns tPD Industrial

MACH130

Contextual Info: F IN A L COM’L: -15/20 IND: -18/24 MACH130-15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ ■ 4 “PAL26V16” Blocks

Contextual Info: — / FINAL ▼ V A N A N A M D COM'L: -15 MACH4-96/96-15 T I S High-Performance EE CMOS Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 144 Pins in PQFP 96 Macrocells 15 ns t PD 47.6 MHz fCNT 102 Inputs with pull-up resistors