PAL26V16 Search Results

MACH130-20

Abstract: MACH130 MACH230 PAL22V10 PAL26V16
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

PAL26V16

Abstract: teradyne lasar
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 Z I Advanced Micro Devices M A C H 1 3 0 - 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ 15 ns tpD Commercial

Contextual Info: FINAL COM’L: -7.5/10/12/15/20 a Advanced Micro Devices M A C H 1 3 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • ■ ■ ■ ■ Programmable power-down mode 64 Outputs 64 Flip-flops; 4 clock choices

Contextual Info: CO M ’L: -5/7.5/10/12/15/20 M A C H 1 11 -5 /7 /1 0 /1 2 /1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Program m able power-down mode ■ 32 M acrocells ■ ■ 5 ns tpD ■ 32 Flip-flops; 4 clock choices

PAL26V16

Abstract: MACH130-20 PAL 007 64 macrocells PAL 007 A MACH130 MACH230 PAL22V10 MACH130-20/BXA
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice/Vantis High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

mach 3 family amd

Abstract: circuit diagram of QS 8005 PAL26V16 D750 MACH110 MACH210 MACH215 PAL22V10 mach 1 family amd NS4N
Contextual Info: FINAL COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24 M A C H 2 1 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic Z I Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 64 Macrocells ■ Programmable power-down mode ■ 32 Outputs

Contextual Info: CO M ’L : -15/20 M IL :-20 MACH230-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins 70 Inputs ■ 128 M acrocells 64 Outputs ■ 15 n stpD Com m ercial 128 Flip-flops; 4 clock choices 20 ns tPD M ilitary

Contextual Info: bOE D • D S 5 7 5 2 b D0 33 D3 5 3QS AMDS ADV MICRO P L A / P L E / A R R A Y S COM’L: -15/20 MIL: -20 M A C H 1 3 0 -1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS ■ 84 Pins ■ 70 Inputs ■ 64 Macrocells

Contextual Info: PRELIMINARY M ACH COM’L: -7/10/12/15/20 a 1 1 1 - 7 /1 0 /1 2 /1 5 /2 0 Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Outputs ■ 32 Macrocells ■ 32 Flip-flops; 4 clock choices ■ 7.5 ns tpD

Contextual Info: FIN AL M A C H 1 1 1 COM’L: -5/7.5/10/12/15/20 IND: -7.5/10/12/14/18/24 AM D£t F a m ily High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Programmable power-down mode ■ 32 Macrocells ■ 32 Outputs ■ 5 ns tPD ■ 32 Flip-flops; 4 clock choices

MACH110 cross reference

Abstract: PAL 002a MACH Technical Briefs Manual PAL 008a ACH110 amd 44 MACH210 class B
Contextual Info: a MACH Family Data Book High Density EE CMOS Programmable Logic Summer 1992 A d van ced Micro Devices M ACH™ 1 and M ACH 2 F a m ilie s High Density EE CMOS Programmable Logic Q3 1992 Data Book Final: Preliminary: M AC H 110-12/15/20 C om ’l, Mil M ASC 110-15/20 C om ’l

O-81-4

Abstract: MACH211SP MACH110 MACH111SP PALCE22V10 MACH111SP-10JC PALCE* programming
Contextual Info: FINAL COM’L: -5/7.5/10/12/15 IND: -7.5/10/12/14/18 MACH111SP-5/7/10/12/15 High-Density EE CMOS Programmable Logic V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS • JTAG-Compatible, 5-V in-system programming ■ Programmable power-down mode

Contextual Info: PRELIM INARY COM’L: -7/10/12/15/20 Z I Advanced Micro Devices M A C H 1 3 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ 7.5 ns tpo

Contextual Info: F IN A L COM’L :-10/15/20 IND:-18/24 a Advanced Micro Devices M A C H 2 3 0 - 1 0 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 128 Macrocells ■ 128 Flip-flops; 4 clock choices ■ 10 ns tpD Commercial

MS1028

Abstract: MACH130-20 MACH130 teradyne lasar MACH230 PAL22V10 mach 1 to 5 from amd MACH Programmer mach 1 family amd PAL26V16
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 Advanced Micro Devices MACH130-15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

PPI-0223

Abstract: MACH130 PALCE22V10 Tag c0 665 800 MACH131sp
Contextual Info: PRELIMINARY COM’L: -5/7.5/10/12/15 IND: -7.5/10/12/14/18 MACH131SP-5/7/10/12/15 High-Density EE CMOS In-System Programmable Logic V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS • JTAG-compatible, 5-V in-system programming

BP1148

Abstract: MACH111-20JC MACH110 MACH210 MACH215 PAL22V10
Contextual Info: FINAL COM’L: -5/7.5/10/12/15/20 IND: -7.5/10/12/14/18/24 MACH111 Family High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Programmable power-down mode ■ 32 Macrocells ■ 32 Outputs ■ 5 ns tPD ■ 32 Flip-flops; 4 clock choices

Contextual Info: COM’L: -15/20 a MACH230-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 128 Macrocells ■ 128 Flip-flops; 4 clock choices ■ 15nstPD ■ 8 “PAL26V16” blocks with burled macrocells

Contextual Info: FINAL COM’L : -10/15/20 IN D :-18/24 Lattice/Vantis M A C H 2 3 0 - 1 0 /1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins 64 Outputs ■ 128 Macrocells 128 Flip-flops; 4 clock choices ■ 10 ns tpD Commercial 8 “PAL26V16” blocks with buried macrocells

Contextual Info: FINAL IND: -10/12/14/18/24 COM’L: -7.5/10/12/15/20 a Advanced Micro Devices M A C H 2 1 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 64Macrocells ■ Programmable power-down mode ■ 7.5 ns î p d Commercial

Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH230-15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 70 Inputs ■ 128 Macrocells ■ 64 Outputs ■ 15 ns tpD Commercial 18 ns tpD Industrial ■ 128 Flip-flops; 4 clock choices

gg3b

Contextual Info: FINAL COM’L: -5/7.5/10/12/15/20 a Advanced Micro Devices M A C H 1 11 -5 /7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Programmable power-down mode ■ 32 Macrocells ■ 32 Outputs ■ 5 ns tpD

Contextual Info: FINAL COM’L: -15/20 IND: -18/24 & M A C H 13 0 -1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 70 Inputs ■ 64 Macrocells ■ 64 Outputs ■ 15 ns tPD Commercial I S n s t p D Industrial

PAL 007 E

Abstract: PAL 007 B 84 pin plcc lattice dimension PAL 007 PAL 007 A PAL 007 c MACH130 MACH230 PAL22V10
Contextual Info: FINAL COM’L: -10/15/20 IND: -18/24 MACH230-10/15/20 Lattice/Vantis High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 128 Macrocells 128 Flip-flops; 4 clock choices 10 ns tPD Commercial 18 ns tPD Industrial 8 “PAL26V16” blocks with buried macrocells