PALCE61 Search Results

Contextual Info: Ml intpl 6 1992 ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Extensive Software and Programming Support via Intel and Third Party Tools

EP610

Abstract: PALCE610 CE610H
Contextual Info: FINAL COM’L: H-15/25 PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

PLD610-10

Abstract: 85C060 D610 p EP610 "pin compatible" PLD610
Contextual Info: PLD610 PRELIMINARY CYPRESS SEMICONDUCTOR Multipurpose BiCMOS PLD Function, pin, and JEDEC compatible with EP600, EP610, EP630,85C060, and PALCE610 PLDs Very high performance — tpo = 10 ns 16 I/O macrocells, each having: — Choice of combinatorial or regis­

D85C060-25

Abstract: PLD610 85C060 P85C060-25 PLD610-25 P85C060-15 D85C060-10 intel 85C060 n85c060 pld610-15
Contextual Info: intel ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610, 85C060 and 5C060 PLDs • tpD 10 ns, 100 M H z C o u n te r F req u en cy w /ln te rn a l F e e d b a c k ■ E xte n s ive S o ftw a re an d P ro g ram m in g

npld610

Abstract: NPLD610-10 PALCE610 EP610 ORDERING PLD610 DPLD610-25 intel 85C060 85C060 TNPLD610 intel PLD
Contextual Info: in tj ¡PLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • * m - m r ' "< ^ . *. » • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 m A max-@ 1 MHz

Contextual Info: AMDH COM’L: H-15/25 PALCE610 Family EE CMOS High Performance Programmable Array Logic ?. *.? eoV . . s DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

12950-012a

Abstract: pal 007a si 13003 al 13003 pal 005a 13003 application notes pal 003A pal 010a 13003 circuit 13003 d
Contextual Info: COM’L: H-15/25 MIL: H-20 PALCE610 Family Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

DPLD610-15

Abstract: npld610 iPLD610 PPLD610-25 PPLD610 TNPLD610 DPLD610-10 intel 85C060 NPLD610-10 PLD610
Contextual Info: in t e i ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Com patible wKh EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 mA max- @ 1 MHz ■ Programmable Low-Power Option for

d6105

Contextual Info: PLD610 PRELIMINARY OYPRESS SEMICONDUCTOR • Function, pin, and JEDEC compatible with EP600, EP610, EP630,85C060, and PALCE610 PLDs • Veiy high performance — tpo = 10 ns • 16 I/O macrocells, each having: — Choice of combinatorial or regis­ tered output

Pal programming

Abstract: EP610 PALCE610 EP610 ORDERING EP610 "pin compatible"
Contextual Info: COM’L: H-15/25 Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

EP610

Abstract: PALCE610 sr flipflop
Contextual Info: USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-15/25 Lattice Semiconductor PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Lattice/Vantis Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or

Contextual Info: NOV 2 1 199! MIL: -20 COM’L: -15/25 ÍI PALCE61 OH-15/25 Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or

P85C060-25

Abstract: D85C060 PLD610-25 D85C060-25 intel 85C060 D85C060-15 IPLD610-15 EP610 ORDERING p85c060 N85C060-12
Contextual Info: INTEL CORP tIEMORY/PLD/ in t e l SbE D • HfiSblTb D077infl fl3£ ^p ÌPLD610/85C060 FAST 16-MACROCELL CMOS PLD h ITL2 ^ '^ - o 0 Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs ■ tpo 10 ns, 100 MHz Counter Frequency

str 5717

Abstract: pal 007a 617-2240 4558 pin configuration PAL 002a 13003 TO 92 PACKAGE 4155 cmos cd 13003 pal 003A pal 005a
Contextual Info: NOV 2 1 199! COM’L: -15/25 M IL :-20 El Advanced Micro Devices PALCE61 OH-15/25 EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or

Contextual Info: COM’L: H-15/25 MIL: H-20 Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

TI EP610

Contextual Info: PALCE610 Family AdVMi“ro EE CMOS High Performance Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins ■

Contextual Info: COM’L: H-15/25 MIL: H-20 H Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: FINAL AMDÌ1 COM’L: H-15/25 PALCE610 Family V A RI T I EE CMOS High Performance Programmable Array Logic AN A M D C O M P A N Y DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or

PALCE610H-25

Abstract: EP610 PALCE610 lattice 1996
Contextual Info: FINAL COM’L: H-15/25 Lattice/Vantis PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Lattice/Vantis Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: FINAL COM’L: H-15/25 Lattice/Vantis PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Lattice/Vantis Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: COM’L: H-15/25 MIL: H-20 SI PALCE610 Family Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

85c060

Abstract: intel iPLD610 pld610 P85C060-25 D85C060-15 EP610 ORDERING intel 85C060 intel PLD 29045 EP610 "pin compatible"
Contextual Info: in tJ . ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tPD 10 ns, 100 MHz C ounter Frequency w /ln tern al Feedback ■ Extensive Softw are and Programming

12950-012a

Contextual Info: Preliminary COM’L i PALCE61 OH-15/25 l Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

12950G

Contextual Info: COM'L: H-15/25 FINAL PALCE610 Family AdvaM Tro EE CMOS High Performance Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins