MSL260G
Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Text: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)
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PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
MSL260G
MSL-260-G
D0806
R0807
T0803
D0802
D0807
RDD0804
D0808
5 pin reset ic ARB
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UPD720101GJ-UEN
Abstract: UPD720101 34c72 787616-1 NEC AMC OSC48MHz AD27 AD29 AD30 NEC A61
Text: 4 3 5V 3.3V AD17 CBE20 C IRDY0 DEVSEL0 PERR0 SERR0 CBE10 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 AD18 AD16 FRAME0 TRDY0 STOP0 PAR AD15 AD13 AD11 3.3V 1 36 1% 2 1 R54 36 1% 2 1 RSDM4 DM4 DP4 RSDP4 132 133 135 136 R57 36 1% 2 1 R56 36 1% 2 1 RSDM5 DM5 DP5 RSDP5 138
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CBE20
CBE10
R67egulator
uPC29L33T
150uF
BLM21PG600SN1
uPD720101
ET-0143D)
ISG-2UE-00070
UPD720101GJ-UEN
34c72
787616-1
NEC AMC
OSC48MHz
AD27
AD29
AD30
NEC A61
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la1 d22
Abstract: la2 d2 timer rn0805 U0301 L16 eeprom 80960CA LD11 LD12 U0101 PCI9060 68040
Text: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH |P8.SCH
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U0101
PCI9060,
80960CA
U0102
20V8R
PCI9060
PCI9060/68040
la1 d22
la2 d2 timer
rn0805
U0301
L16 eeprom
LD11
LD12
U0101
PCI9060 68040
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Y0803
Abstract: U0801B IC LM7805 N1 Y10 pin diagram of IC LM7805 C0801 STI3400 U0101 U0604 plx9060
Text: Q CL 7 D PR 3 4 14 2 U?A Q 5 CLK 6 {Value} 1 1 2 3 4 5 6 SPARE GATES: 8 ECN HISTORY DESCRIPTION REV 2 -ADD CDREQ DATE APPROVAL 10/24/95 U0101 PU0101 A PU0102 PU0103 12 11 D U0801B 9 Q CLK 8 Q 74ACT74 13 20V8C DIP 22 21 20 19 18 17 16 15 CL O1 IO2 IO3 IO4 IO5
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U0101
PU0101
PU0102
PU0103
U0801B
74ACT74
20V8C
PU0104
Y0803
U0801B
IC LM7805
N1 Y10
pin diagram of IC LM7805
C0801
STI3400
U0101
U0604
plx9060
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mah8
Abstract: MDL22 u0502a LD11 LD12 U0101 RN05 RN0501 U0302
Text: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH 7
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U0101
PCI9060,
9060/DRAM
U0102
20V8R
PCI9060
PCI9060/DRAM
mah8
MDL22
u0502a
LD11
LD12
U0101
RN05
RN0501
U0302
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L1239
Abstract: l0728 l0312 SGS L282 L0936 L11616 L9960 0x00000404 L1198 L1322
Text: Go to next Section: PCI to Local Bridge Performance Study Return to Table of Contents Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PCI 9060/MPEG AN January 14, 1996 MPEG to PCI bus Application Note _ _ _
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9060/MPEG
L1239
l0728
l0312
SGS L282
L0936
L11616
L9960
0x00000404
L1198
L1322
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D0807
Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
Text: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors
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PCI9060
PCI9060,
80960CA
82596CA
U0101
20V8R
U0102
PCI9060
D0807
C0702
D0801
D0806
R0807
T0803
D0808
D0802
RDD0804
C0705
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PDF
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16V8-10
Abstract: U0801A
Text: PowerPC 403 to PCI 9060ES Application Note PCI 9060/403 AN May 10, 1996 Version 0.4 PowerPC 403 to PCIbus Application Note Features_ • • • • Embedded system containing PowerPC 403 with a PCIbus interface PCI 9060ES chip supports master, slave and PCI
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9060ES
9060ES
403local
403GC
PCI9060ES
100ns
150ns
200ns
16V8-10
U0801A
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UPD720101
Abstract: fb11 OSC48MHz A11136 UPD720101F1-EA8 AD27 AD29 AD30 osc48m ISG-2UE-00071
Text: 4 3 5V 3.3V AD17 CBE20 C IRDY0 DEVSEL0 PERR0 SERR0 CBE10 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 PAR FRAME0 IRDY0 TRDY0 STOP0 IDSEL DEVSEL0 REQ0 GNT0 PERR0 SERR0 INTA0 INTB0 INTC0 PCLK PCIRST0 PME0 AD18 AD16 FRAME0 TRDY0 STOP0 PAR AD15 AD13 AD11 3.3V 132 96 129
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CBE20
CBE10
uPC29L33T
BLM21PG600SN1
150uF
uPD720101
ET-0143E)
ISG-2UE-00071
fb11
OSC48MHz
A11136
UPD720101F1-EA8
AD27
AD29
AD30
osc48m
ISG-2UE-00071
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68040* part numbering
Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Text: Go to next Section: Designing a PCI Memory Board Return to Table of Contents Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _
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PCI9060/68040
PCI9060
32-bit
PCI9060,
100ns
200ns
300ns
68040* part numbering
93CS46
SR96
L16 eeprom
Motorola 68040
Pal programming
10B5
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PDF
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16V8-10
Abstract: semiconductor ad 5.9 u0304 R0801 74ACT74 LD11 LD12 U0801A LA17 MXA0 A10
Text: ECN HISTORY |LINK |N2.SCH |N3.SCH |N4.SCH |N5.SCH |N6.SCH |N7.SCH SPARE GATES: DESCRIPTION DATE REV 1 - 01/24/96 REV 2 -CHANGED DRMMUX 2/17/96 APPROVAL PU0101 1 PU0102 PU0103 12 11 D P R U0303B Q 9 CLK C L 1 3 Q 8 74ACT74 PU0104 APPROVALS DATE PLX TECHNOLOGY
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PU0101
PU0102
PU0103
U0303B
74ACT74
PU0104
POWERPC/PCI9060ES
220uF
16V8-10
semiconductor ad 5.9
u0304
R0801
74ACT74
LD11
LD12
U0801A
LA17
MXA0 A10
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0x9050 0x10b5
Abstract: 8BA22 LA2780 PLXMON95 10B5 BD28 MACH210 NM93CS46 9050RDK PLX9050
Text: PCI 9050RDK Development Kit Manual Version 1.2 January 28, 1998 Product Sales: 1- 800 -759-3735 Fax: 1- 408-774-2169 Email: info@plxtech.com Web and FTP Site: //www.plxtech.com T E C H N O L O G Y Table of Contents Preface . vii
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9050RDK
9050RDK-M002
0x9050 0x10b5
8BA22
LA2780
PLXMON95
10B5
BD28
MACH210
NM93CS46
9050RDK
PLX9050
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787616-1
Abstract: OSC48MHz NEC A37 PCICON62 NEC AMC UPD720101 NEC A61 A37 diode LT1086CM R58 B48
Text: 3 DEVSEL0 PERR0 SERR0 CBE10 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 PAR FRAME0 IRDY0 TRDY0 STOP0 IDSEL DEVSEL0 REQ0 GNT0 PERR0 SERR0 INTA0 INTB0 INTC0 PCLK PCIRST0 PME0 AD18 AD16 FRAME0 TRDY0 STOP0 PAR AD15 AD13 AD11 3.3V 132 96 129 6 97 92 54 126 144 55 7 125
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CBE10
CBE30
CBE20
CBE00
PCICON62
150uF
BLM21PG600SN1
uPD720101
ET-0143E
787616-1
OSC48MHz
NEC A37
PCICON62
NEC AMC
NEC A61
A37 diode
LT1086CM
R58 B48
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AD14
Abstract: PCICON62B AD27 AD17 AD29
Text: 1 2 3 4 5 6 7 8 A A CLK TDD VCC VCC J0601 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 REQ# AD[0.31] AD[0.31] AD31 AD29 AD27 AD25 B C/BE3# AD23 AD21 AD19 AD17 C/BE2#
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J0601
J0602
REQ64#
PCICON62A
PCI9060/DRAM
AD14
PCICON62B
AD27
AD17
AD29
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la2 d2 timer
Abstract: L0936 Header 13X2 l0728 PIN DIAGRAM OF IC LM7805 U0202 L9960 STI3400 L1239 L4204
Text: Go to next Section: PCI to Local Bridge Performance Study Return to Table of Contents Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PLX Technology SGS PCI MPEG Board Engineering Changes 07/15/96 1. The PCI9060 always reads long words, even when the local bus is configured for 16-bits. Modify the BUSCTL
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PCI9060
16-bits.
la2 d2 timer
L0936
Header 13X2
l0728
PIN DIAGRAM OF IC LM7805
U0202
L9960
STI3400
L1239
L4204
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8BA22
Abstract: header 20X2 PCICON62B ba21 PCI9050 LA10 LA12 LA15 LA16 LA17
Text: A B C D E 2 CLK 2 PAR 2 IDSEL C/BE0# C/BE1# C/BE2# C/BE3# 2 RST# 2 INTA# 2 STOP# 2 PERR# 2 SERR# 2 FRAME# 2 DEVSEL# 2 IRDY# 2 TRDY# 2 LOCK# 2 2 2 2 2 AD[31.0] E 5V E 1 5 8 4 1 R2 2 2 10k R1 10k PE PRE CS SK DI GND VCC DO U3 93CS46 1 2 JUMPER JP3 5V 6 7 1
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93CS46
IRQ12
IRQ15
IRQ14
MSTR16#
ISA16B
9050RDK
74AC20
8BA22
header 20X2
PCICON62B
ba21
PCI9050
LA10
LA12
LA15
LA16
LA17
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AD14
Abstract: AD27 PCICON62B AD-12 AD17 AD29 AD12 J0701
Text: 1 2 3 4 5 6 7 8 2 CLK TDD VCC VCC J0701 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 A 2 2 REQ# AD[0.31] AD[0.31] AD31 AD29 2 AD27 AD25 C/BE3# AD23 AD21 AD19 B AD17
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J0701
J0702
AD2N62B
PCICON62A
AD14
AD27
PCICON62B
AD-12
AD17
AD29
AD12
J0701
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AD14
Abstract: PCICON62B electronic lock schematic diagram AD-12 AD11 AD17 AD27 AD29 AD252 AD10
Text: CLK 2 INTA# 2 RST# 2 GNT# 2 IDSEL 2 TDD VCC VCC J0601 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 +3.3V 2 2 REQ# AD[0.31] AD[0.31] AD31 AD29 AD27 AD25 2 C/BE3#
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J0601
REQ64#
PCICON62A
POWERPC/PCI9060ES
AD14
PCICON62B
electronic lock schematic diagram
AD-12
AD11
AD17
AD27
AD29
AD252
AD10
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1N4148/2 pin connector sip
Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
Text: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000
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PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
1N4148/2 pin connector sip
ACT04 MOTOROLA
1N4148 D0805
pal programming
sw dip-3
80960CA
15 pin through hole d sub connector
16v8h
DIODE MOTOROLA B33
D0805
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L0936
Abstract: L0988 L9960 L1239 STI3400 L1462 E442 L1105 L3216 U0601
Text: Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PCI 9060/MPEG AN January 14, 1996 MPEG to PCI bus Application Note _ _ _ General Description _ Features_
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9060/MPEG
L0936
L0988
L9960
L1239
STI3400
L1462
E442
L1105
L3216
U0601
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PDF
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10B5
Abstract: 93CS46
Text: Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • •
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PCI9060/68040
PCI9060
32-bit
PCI9060,
100ns
200ns
300ns
10B5
93CS46
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MPC860
Abstract: PCI9080 mpc860 users manual "Development Support" 9080RDK-860 0x10b5 DY9080 R9080 32X2 BUS49 LA10
Text: PCI 9080RDK-860 Hardware Reference Manual Release 2.0, initial publishing February 2, 1998. Copyright 1998, PLX Technology, Inc. All rights reserved. This document contains proprietary and confidential information of PLX Technology Inc. PLX . The contents of this document may not be copied nor duplicated in any form, in whole or in part,
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9080RDK-860
MPC860
PCI9080
mpc860 users manual "Development Support"
0x10b5
DY9080
R9080
32X2
BUS49
LA10
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uPD720102
Abstract: UPD720102GC UPD720102GC-YEB-A CBE20 UPD720102GC-YEB ET-D720102-0002 D7201 D720102 NEC A37 AD27
Text: 3 Connect PCI PRSNT1# and PRSNT2# pins to GND appropriately to correctly reflect the total card power consumption. AD12 AD10 AD8 AD7 AD5 AD3 AD1 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 AD8 AD7 +3.3V AD5 AD3 GND AD1 VDD_IO ACK64# +5V +5V C/BE0# +3.3V AD6
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CBE10
ACK64#
REQ64#
CBE30
CBE20
CBE00
uPD720102
UPD720102GC
UPD720102GC-YEB-A
CBE20
UPD720102GC-YEB
ET-D720102-0002
D7201
D720102
NEC A37
AD27
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code h7f
Abstract: datasheet LD9 m mah8 MDL22 MDL14 fuse 9060ES A3-12 LD11 MACH210A U0101
Text: Go to next Section: PowerPC 403 to PCI 9060ES Return to Table of Contents Designing a PCI Memory Board No CPU, DRAM Control examples PLX PCI9060 DRAM Controller Application Note Revision 1.0 September 8, 1995 PLX Technology, Inc. 625 Clyde Avenue, Mt View, California 94043
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9060ES
PCI9060
9060/DRAM
100ns
150ns
PCI9060
BCLK-33
code h7f
datasheet LD9 m
mah8
MDL22
MDL14 fuse
9060ES
A3-12
LD11
MACH210A
U0101
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