PHL PHL 8 26 Search Results

Contextual Info: INTEL CORP UP/PR PHL S 44E D E3 4ö2bl7S 0104S11 2 E3ITL1 [P G & flG Ä » 87C196KB/87C198KB16 HIGH PERFORMANCE CHMOS MICROCONTROLLER 8 Kbytes of On-Chip EPROM 232 Byte Register File Dynamically Configurable 8-Blt or 16-Bit Buswidth Register-to-Register Architecture

74AC11544D

Abstract: 74AC11544N 74ACT11544D 74ACT11544N 74ACT11544
Contextual Info: Philips Components— Signetics Document No. 853-1500 ECN No. 00731 Date of Issue October 17,1990 Status Product Specification AC L Products • Com bines '245 and '373 type func­ tions in one chip 8-bit octal transceiver with D-type latch SYMBOL tpuV l PHL

CP4020

Abstract: 4000B 74HC 74HCT
Contextual Info: 74HC/HCT40103 MSI 8-BIT SYNCHRONOUS BINARY DOWN COUNTER FEA T U R E S TYPICAL SYMBOL Cascadable Synchronous or asynchronous preset Output capability: standard PARAMETER CONDITIONS *PHL/ tPLH propagation delay CP to TC G E N E R A L D ES C R IPTIO N V ia x

Contextual Info: CD4068B Types Features: C M O S 8-Input NAND/AND Gate • Medium-Speed Operation: <PHL. tpL H “ 75 ns typ. at V d d - 1 0 V ■ Buffered inputs and outputs ■ 5-V, 10-V , and 15-V parametric ratings ■ Standardized symmetrical output characteristics

HTGB

Contextual Info: ^ Te x a s In s t r u m e n t s CD4068B Types Data sheet acquired from Harris S em iconductor S C H S053 CMOS 8-Input Features: • Medium-Speed Operation: *PHL- l PLH = 75 ns typ. at V q d = 10 V ■ Buffered inputs and outputs ■ 5-V, 10-V, and 15-V parametric ratings

A6N136

Contextual Info: SHARP 6N135/6N136 General Purpose Type Photocoupler • Features ■ Outline Dimensions Unit : mm 1. High speed response t PHl , t plh (6N135 (6N136 : MAX. 1 .5 |i s a t R L= 4 .lk i2 ) 0.85 *03 1 .2 * n1. i®t ' : MAX. 0 .8 m sat R l = 1 9 k Q ) 2. High common mode rejection voltage

Contextual Info: 74 A C /A C T 11819 8-Bit Diagnostic/Pipe-Line Register with Parity Even O utput S ig n e tic s ACL Products Objective Specification FEATURES GENERAL INFORMATION • H ig h -sp ee d 8 -b it p a ralle l O u tp u t R eg is ter SYMBOL 'PHL • O u tp u t c a p a b ility : ± 2 4 m A

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

7129 equivalent IC

Abstract: 9N74 SN74S136
Contextual Info: TTL MSI TYPES SNS4S13S, SN74S13S QUADRUPLE EXCLUSIVEOR/NOR GATES B U L L E T I N N O . D L-S 721 18 26 . D E C E M B E R 1972 • Fully Compatible with Most T T L and T T L MSI Circuits • Fu lly Schottky Clamping Reduces Delay Tim es . . . 8 ns Typical •

Contextual Info: sony . CXB1142Q/Q-Y Quad 4: 1 Multiplexer with Latch Description Pin Assignment Doe Ooc Doo n n n 24 25 23 D ia O ib 22 21 20 19 D ja Die n n 17 18 I] 26 18 So Q 27 15 ^ *'E 28 14 ~~| V c c* ^ ^ ^ VCCA • Typical propagation delay time: Tpd=830ps DnA-DnD to Qn

sh 2089

Abstract: 925 590-2 STD130 TF 2309 CL 0805 2.4964
Contextual Info: INPUT BUFFERS Cell List Cell Name Function Description PIC/PICD/PICU 1.8V Interface CMOS Level Input Buffers PMIC/PMICD/PMICU 2.5V Interface CMOS Level Input Buffers PHIC/PHICD/PHICU 3.3V Interface LVCMOS Level Input Buffers PTIC/PTICD/PTICU 3.3V-tolerant for 1.8V Interface CMOS Level Input Buffers

application notes of TF 513

Abstract: PHSOSCK17 PHSOSCK27 STD130
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

CL 2181

Abstract: SL 1088 PHSOSCK17 PHSOSCK27
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

CL 2182

Abstract: CL 1221 cl 5403 A 1908 SL 2042 CMOS 4039
Contextual Info: INPUT BUFFERS Cell List Cell Name Function Description PIC/PICD/PICU 1.8V Interface CMOS Level Input Buffers PMIC/PMICD/PMICU 2.5V Interface CMOS Level Input Buffers PHIC/PHICD/PHICU 3.3V Interface LVCMOS Level Input Buffers PTIC/PTICD/PTICU 3.3V-tolerant for 1.8V Interface CMOS Level Input Buffers

inverter PURE SINE WAVE schematic diagram

Abstract: sine wave inverter schematic IVT HS 400 PURE SINE WAVE inverter schematic diagram sine wave inverter using pic schematic diagram ac-dc inverter tda 12155 r 4366 1 phase pure sine wave inverter schematic oa31 diode CL-21 capacitor
Contextual Info: Revision History - First Edition: March 1999 - Second Edition: February 2000 • Library name change MDL110 into STD110 • All characteristic values are updated with mass product line characteristics. • Add high density compiled memories to second edition. chapter 5

TDA 7378

Abstract: TDA 7822 block diagram baugh-wooley multiplier tda 12062 equivalent for tda 4858 ic free transistor equivalent book STD-80 4856 a 14 PIN DIP W908 LSI CMOS Technology
Contextual Info: D • A • T • A • B • O • O • K STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library April 1997 V SAMSUNG SAMSUNG ASIC STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library Data Book  1997 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior

TDA 8369

Abstract: circuit integrate tda 7283 B764E sine wave inverter schematic IVT HS 400 S901E tda 0470 TDA 7277 TDA 9394 tda 7283 CPU 414-2 Processor Module
Contextual Info: STDM110 0.25µm 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products STDM110 0.25µm 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products Data Book  1999 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior

SL 220 YN 2

Abstract: MX2D2
Contextual Info: BUSHOLDER Cell List Cell Name BUSHOLDER Function Description Bus Holder Logic Symbol Cell Data Input Load SL Y 5.7 Y STD131 3-340 Gate Count 1.33 Samsung ASIC INTERNAL CLOCK DRIVERS Cell List Cell Name Function Description CK2 Internal Clock Driver CMOS 2mA

PURE SINE WAVE inverter schematic diagram

Abstract: sine wave inverter schematic IVT HS 400 inverter PURE SINE WAVE schematic diagram microcontroller 1 phase pure sine wave inverter 1 phase pure sine wave inverter schematic OA32 diode 4558 opamp schematic 13001 TRANSISTOR grid tie inverters circuit diagrams wallace-tree VERILOG
Contextual Info: Revision History - First Edition: March 1999 - Second Edition: February 2000 • Library name change MDL110 into STD110 • All characteristic values are updated with mass product line characteristics. • Add high density compiled memories to second edition. chapter 5

SL 2042

Abstract: CL 2181 27570 TR-2207 PHSOSCK17 STD150 TF011 CL118 CL 0805 samsung 1622
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PMSCKDC 2/4/6/8 2.5V CMOS Level Input Clock Driver PMSCKDCD(2/4/6/8) 2.5V CMOS Level Input Clock Driver with Pull-Down PMSCKDCU(2/4/6/8) 2.5V CMOS Level Input Clock Driver with Pull-Up PMSCKDS(2/4/6/8)

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 - D32Q0, OCTOBER 1989 - REVISED APRIL 1993 • ■ I ■ I * Inputs Are TTL-Voltage Compatible * New Flow>Through Architecture Optimizes PCB Layout * Center-Pin V ^c and GND Configurations Minimize High-Speed Switching Noise

tda 9592

Abstract: TDA 2310 verilog code for Modified Booth algorithm tda 7830 TDA 8344 sl 7221 KGL80 AO33 FD2S
Contextual Info: D • A • T • A • B • O • O • K KGL80 0.5µm 3.3V Gate Array Cell Library April 1997 V SAMSUNG SAMSUNG ASIC KGL80 0.5µm 3.3V Gate Array Cell Library Data Book  1997 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior

TDA 3619

Abstract: Data sheet TDA 3619 TDA 8701 AN star delta FORWARD / REVERSE WIRING CONNECTION tda 9592 OA2222L TDA 810 amplifier sm 4109 TAG 8907 TDA audio power amplifier
Contextual Info: Revision History Based on Hard Copy . - 1’st Edition(V1.0) : April. 2003 • Chapter 1 : Introduction • Chapter 2 : DC Electrical Characteristics(Recommended Operating Conditions) • Chapter 3 : Primitive Cells • Chapter 5 : Compiled Memories STDL130

circuit diagram of inverting adder

Abstract: STDH150
Contextual Info: BUSHOLDER Cell List Cell Name BUSHOLDER Function Description Bus Holder Logic Symbol Cell Data Input Load SL Y 5.6 Y Samsung ASIC 3-367 Gate Count 1.67 STDH150 ADDERS Cell List Cell Name Function Description FA Full Adder with 1X Drive FAD2 Full Adder with 2X Drive