PM5333 Search Results

TUG-3

Abstract: PM5397 PM4319 vc-4 digital cross connect
Contextual Info: PM5333 ARROW 8xFE Preliminary 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device FEATURES • Supports loss-less IEEE 802.3 local flow-control. • Provides per port Ethernet Statistics using 32-bit counters for frames and 40-bit counters for octets to ensure

Contextual Info: PM5333 ARROW 8xFE Preview 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device FEATURES • Supports loss-less IEEE 802.3 local flow-control. • Provides per port Ethernet Statistics using 32-bit counters for frames and 40-bit counters for octets to ensure

Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device PM r, 20 04 09 :2 1: 26 • Supports the following encapsulation protocols on a per port basis: • ITU-T G.7041 Generic Framing Procedure frame-based . • ITU-T X.86 Link Access Procedure

vc-4 digital cross connect

Abstract: DSA0056825
Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device PM ,2 00 7 09 :4 5: 09 • Supports the following encapsulation protocols on a per port basis: • ITU-T G.7041 Generic Framing Procedure frame-based . • ITU-T X.86 Link Access Procedure

Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device AM y, 20 05 09 :3 0: 09 • Supports the following encapsulation protocols on a per port basis: • ITU-T G.7041 Generic Framing Procedure frame-based . • ITU-T X.86 Link Access Procedure

Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device PM 20 05 08 :4 9: 15 • Supports the following encapsulation protocols on a per port basis: • ITU-T G.7041 Generic Framing Procedure frame-based . • ITU-T X.86 Link Access Procedure

Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device AM r, 20 04 02 :4 5: 42 • Supports the following encapsulation protocols on a per port basis: • ITU-T G.7041 Generic Framing Procedure frame-based . • ITU-T X.86 Link Access Procedure

Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device PM ,2 00 5 08 :2 2: 26 • Supports the following encapsulation protocols on a per port basis: • ITU-T G.7041 Generic Framing Procedure frame-based . • ITU-T X.86 Link Access Procedure

vc-4 digital cross connect

Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device ,1 ay sd ne ed W n co ETHERNET SUBSYSTEM Pa rtm in er In • Provides integrated IEEE 802.3 compliant media access controllers MAC . • Provides IEEE 802.3 compliant Ethernet

Contextual Info: PM5333 ARROW 8xFE Released 8 Channel 10/100 Ethernet over SONET/SDH Mapping Device PM t, 20 05 01 :1 3: 56 • Supports the following encapsulation protocols on a per port basis: • ITU-T G.7041 Generic Framing Procedure frame-based . • ITU-T X.86 Link Access Procedure

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect LB_IFP[4:1] rtm LBTE x4 R_P/N [26] R_P/N [27.74] LB_ECLK[4:1] RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx DMI ESSI Tx RASIO 3G Tx ESSI Tx RASIO 3G Tx ESSI Tx RASIO

CROSS-CONNECT

Abstract: PM5326 PM5397 PM5369 PM5377 PM5389 TU12 WSE20
Contextual Info: PM5389 WSE 20 Released SONET/SDH Wideband Cross-Connect FEATURES GENERAL • Multi-purpose SONET/SDH VT/TU and SONET/SDH STS/STM cross-connect. • With a memory-switch architecture, implements a strictly non-blocking switch that supports a VT/TU level fabric of up to 25 Gbit/s.

PM5326

Abstract: PM5377 STS192 STS-48
Contextual Info: PM5377 TSE 240 Released Single Chip 96-Port STS-1/STM-0 Cross-Connect FEATURES DELAY MANAGEMENT • Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity. • 96 ingress and 96 egress STS48/STS-12 ports for a maximum of 4608 STS-1/AU-3 streams in a single

PM5326

Abstract: PM5324 PM5377 STS192 STS-48
Contextual Info: PM5377 TSE 240 Advance Single Chip 96 Port SONET/SDH Cross-Connect Switch Element FEATURES TOH PROCESSING AND TESTING • Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity. • 96 ingress and 96 egress STS48/STS-12 ports for a maximum of

OC-192/STM-64

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION co LB_IFP[4:1] n LB_ID[4:1][1:0] 17 7: :0 Th BLOCK DIAGRAM LB_ED[4:1][1:0] LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ICLK[4:1] er In LB_ECLK[4:1] R_P/N [26] R_P/N [27.74]

Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect SWITCH PORT CONFIGURATION LB_ID[4:1][1:0] 37 5: :3 LB_ED[4:1][1:0] LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ECLK[4:1] rtm in LB_ICLK[4:1] er LB_IFP[4:1] of Pa R_P/N [1.25] R_P/N [26] m ea

Contextual Info: PM5308 TSE 120 Released PM Single Chip 74-Port STS-1/STM-0 Cross-Connect TOH PROCESSING AND TESTING co LB_IFP[4:1] of 13 1: :4 LBTO x4 LB_EFP[4:1] LBTE (x4) LB_ICLK[4:1] er In LB_ECLK[4:1] tm in R_P/N [1.25] R_P/N [26] R_P/N [27.74] RASIO 3G Rx ESSI Rx

Contextual Info: PM5308 TSE 120 Released AM Single Chip 74-Port STS-1/STM-0 Cross-Connect TOH PROCESSING AND TESTING rtm LB_IFP[4:1] 51 4: LB_EFP[4:1] LBTE x4 of Pa LB_ECLK[4:1] m R_P/N [1.25] R_P/N [26] R_P/N [27.74] RASIO 3G Rx ESSI Rx RASIO 3G Rx ESSI Rx RASIO 3G Rx