QL16X24B Search Results

16X24B

Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

PL84

Abstract: ql16x24bl PF100 PF144
Contextual Info: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

QL4090

Abstract: pASIC 1 Family 160CQFP 208-CQFP
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

16X24

Contextual Info: QL16x24B/QL16x24BH WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS B Very High Speed - V iaL ink metal-to-metal program m able-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

Contextual Info: QL16x24B CMOS FPGA WildCat Series Low Power 3.3 Volt Operation ADVANCE DATA 3.3 VOLT pASIC HIGHLIGHTS High Speed pASIC 1 FPGA Architecture - Enables very high­ performance operation at 3.3 Volts e.g., datapath speed up to 80 MHz at 3.3V . 5 Very low-power operation - Typical Icc is 250|iA.

Contextual Info: I/O Buffer Information QL8x12B, QL12x16B, QL16x24B Components: QL8x12B, QL12x16B, QL16x24B Signals: All I/O pins. Please contact the QuickLogic Hotline 408 990-4100 for more information. IOL Min -24.3 -23.4 -22.5 -21.6 -20.7 0.0 18.9 35.6 47.3 54.9 58.5

QuickLogic ql16x24b-1pl84c

Abstract: QL16X24B PF144 cmos io QL16X24BH TQFP 144 PACKAGE CF160 PF100 PL84
Contextual Info: QL16x24B/QL16x24BH Wild Cat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B .4000 usable gates, 122 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

Contextual Info: QL16x24B Wildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev A pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 16-by-24 array of384 logic cells provides 12,000

CF160

Abstract: PF100 PF144 PL84
Contextual Info: QL16x24B 5.0V pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns at 5V, and over 80 MHz at 3.3V operation.

Contextual Info: QL16X24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins S 5V Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and bipolar devices by sinking up to 12 mA see IIH specification . S High Usable Density - A 16-by-24 array of 384 logic cells

CPGA144

Contextual Info: QL16X24B pASIC 1 FAMILY Very-High-Speed 4K 12K Gate CMOS FPGA PRELIMINARY DATA pASIC HIGHLIGHTS .4000 usable gates, 122 input pins B Very High Speed - ViaLink metal-to-metal programmable-via anti­ fuse technology, allows data path speeds over 150 MHz, and logic cell

Contextual Info: QL16x24B CMOS FPGA WildCat Series Low Power 3.3 Volt Operation ADVANCE DATA 3.3 VOLT pASIC HIGHLIGHTS s Very low-power operation - Typical Icc is 250|aA. 5 4000 usable-gate FPGA - The standard QL16x24B will operate at 3.3V and 5.0 Volts. No special part number.

Contextual Info: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and

CF160

Abstract: PF100 PF144 PL84 QL16X24B-1PF144C
Contextual Info: Appendix E - QL16x24B Pinout Diagrams Appendix E: QL16x24B Pinout Diagrams QL16x24B Packages Summary Total # Pins 84 100 144 144 160 Package Type PLCC TQFP TQFP CPGA CQFP No Connect 2 2 18 VCC and GND 8 12 20 20 20 Clock 2 2 2 2 2 User Pins Input-Only Input/Output

LPKG

Contextual Info: I/O Buffer Information Q L8xl2B, QL12xl6B, QL16x24B Components: QL8x12B, QL12x16B, QL16x24B VOL vs IOL VOH vs lOH V -5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 6.0 7.0 8.0 9.0 10.0 IOH Min -32.4 -30.6 -30.2 -29.7 -28.4 -27.0 -24.8 -22.1 -17.6 -12.6 -6.8

Contextual Info: I/O Buffer Information QL8xl2B, QL12xl6B, QL16x24B Components: QL8x12B, QL12x16B, QL16x24B Signals: All I/O pins. Please contact the QuickLogic Hotline 408 990-4100 for more information. VOL vs IOL IOL Min -24.3 -23.4 -22.5 -21.6 -20.7 0.0 18.9 35.6 47.3

Contextual Info: QL16X24BL W ildCaì 4000L Low Power 3.3 Volt Operation, 4K Gate FPGA High Speed - V ia L in k m etal-to-m etal p ro g ram m a b le -v ia antifuse tech n o lo g y , allow s co u n ter speeds o v er 80 M H z at 3.3 V olt operation. Cl 5V Tolerant I/Os - S u p p o rt in te rfa c e to 5 V o lt C M O S , N M O S and

Contextual Info: QL16x24B/QL16x24BH W ildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B P Very High Speed - V ia L in k inetal-to-metal programmable-via anti­ fuse technology, allows counter speeds over 150 M H z and logic cell delays of under 2 ns. d .4000

Contextual Info: QL16X24B W ild ca t 4000 Very-High-Speed 4K 12K Gate CMOS FPGA pASIC HIGHLIGHTS .4000 usable gates, 122 input pins Q Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

QL16X24B1PF144C

Abstract: CF160 PF100 PF144 PL84 QL16X24B-1PF144C cg144
Contextual Info: Appendix E - QL16x24B Pinout Diagrams Appendix E: QL16x24B Pinout Diagrams QL16x24B Packages Summary Total # Pins 84 100 144 144 160 Package Type PLCC TQFP TQFP CPGA CQFP No Connect 2 2 18 VCC and GND 8 12 20 20 20 Clock 2 2 2 2 2 User Pins Input-Only Input/Output

Contextual Info: QL16X24B CMOS FPGA WildCaX Series Low Power 3.3 Volt Operation ADVANCE DATA 3.3 VOLT pASIC HIGHLIGHTS April 1994 B High Speed pASIC 1 FPGA Architecture - Enables very highperform ance operation at 3.3 Volts e.g., data path speed up to 80 MHz at 3.3V . Q Very low-power operation - Typical Icc is 250|jA.

Contextual Info: I/O Buffer Information QL8x12B, QL12x16B, QL16x24B 2 Components: QL8x12B, QL12x16B, QL16x24B Please contact the QuickLogic Hotline 408 987-2100 for input only (High-Drive) pins. VOL vs IOL IOL Min -24.3 -23.4 -22.5 -21.6 -20.7 0.0 18.9 35.6 47.3 54.9 58.5

QuickLogic ql16x24b-1pl84c

Contextual Info: QL16X24B WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA pASIC HIGHLIGHTS B Very High Speed - ViaLink metal-to-metal programmable-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. H High Usable Density - A 16-by-24 array of 384 logic cells provides

PL84C

Abstract: CPGA Package Diagram TQFP 10 10
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.