QUAZAR Search Results

PAL26V16

Abstract: teradyne lasar
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 Z I Advanced Micro Devices M A C H 1 3 0 - 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ 15 ns tpD Commercial

Contextual Info: FINAL COM’L: -7.5/10/12/15/20 a Advanced Micro Devices M A C H 1 3 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • ■ ■ ■ ■ Programmable power-down mode 64 Outputs 64 Flip-flops; 4 clock choices

mach 3 family amd

Abstract: circuit diagram of QS 8005 PAL26V16 D750 MACH110 MACH210 MACH215 PAL22V10 mach 1 family amd NS4N
Contextual Info: FINAL COM’L: -7.5/10/12/15/20 IND: -10/12/14/18/24 M A C H 2 1 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic Z I Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 64 Macrocells ■ Programmable power-down mode ■ 32 Outputs

Contextual Info: FINAL M A COM'L:-12/15 C H IN D :-18 1 2 0 - 1 2 /1 5 High-Performance EE CMOS Programmable Logic V AN A N A M D T I S C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 68 Pins in PLCC 48 Macrocells 12 ns tpoCommercial, 18 ns tP0 Industrial

1D1010

Abstract: 1D10101
Contextual Info: FINAL COM’L: -10/12/15/20 IND: -14/18/24 Z I Advanced Micro Devices M A C H 2 2 0 - 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 68 Pins ■ 48 Outputs ■ 96 Macrocells ■ 96 Flip-flops; 4 clock choices ■ 10 ns tpD

Contextual Info: FINAL COM’L: -7/10/12/15 IND: -10/12/14/18 VANTI S B E Y O N D P E R FO R M A N C E M A C H 2 2 1 -7 /1 0 /1 2 /1 5 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 68 Pins in PLCC 96 Macrocells

2A299

Abstract: HP3070 MArking 3A5 AMD CPLD Mach 1 to 5 MACH5-256
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND: -10/12/15/20 MACH5-256 MACH5-256/68-7/10/12/15 MACH5-256/120-7/10/12/15 MACH5-256/104-7/10/12/15 MACH5-256/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture

MACH4 cpld amd

Abstract: mach 1 family amd HP3070
Contextual Info: MACH 4 FAMILY 1 MACH 4 Family High Performance EE CMOS Programmable Logic With Maximum Ease Of Use DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ MACH 4 Family ◆ High-performance, EE CMOS CPLD family SpeedLocking for guaranteed fixed timing -7/10/12/15 ns tPD

Contextual Info: 1 MACH 5 FAMILY MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ Publication# 20446 Amendment/0 Rev: D Issue Date: August 1997 MACH 5 Family ◆ Fifth generation MACH architecture — 100% routable

HP3070

Abstract: PALCE22V10
Contextual Info: 1 FINAL MACH 1 & 2 FAMILIES COM’L: -5/7/10/12/15 IND: -7/10/12/14/18 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ 44 Pins in PLCC and TQFP ◆ 32 Macrocells ◆ 5 ns tPD Commercial, 7.5 ns tPD Industrial ◆ 182 MHz fCNT ◆ 32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

MACH111SP

Abstract: MACH465 MACH4-256 mach4256
Contextual Info: MACH 4 FAMILY 1 FINAL COM’L: -10/12/15 IND:-12/14/18 MACH4-256/MACH4LV-256 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 208 pins in PQFP 256 macrocells 10 ns tPD Commercial, 12 ns tPD Industrial

MC189

Abstract: 9300 4b10 2D15 marking 1A15 HP 3D6 1b61a0 MACH5-320 ae 4b15
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-320/MACH5LV-320 MACH5-320/120-7/10/12/15 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15 MACH5-320/184-7/10/12/15

4D-13

Abstract: HP 3D6 making 5A6 3d13 3D-14 5B7 Marking i 384
Contextual Info: MACH 5 FAMILY X FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-384/MACH5LV-384 MACH5-384/120-7/10/12/15 MACH5-384/192-7/10/12/15 MACH5LV-384/184-7/10/12/15 MACH5-384/160-7/10/12/15 MACH5LV-384/120-7/10/12/15 MACH5LV-384/192-7/10/12/15 MACH5-384/184-7/10/12/15

HP3070

Abstract: 1b13 107-2-A-12 MACH5 cpld amd
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND:-10/12/15/20 MACH5-192 MACH5-192/68-7/10/12/15 MACH5-192/104-7/10/12/15 MACH5-192/120-7/10/12/15 MACH5-192/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture

mach231sp

Contextual Info: COM’L: -10/12/15/20 IND: -12/14/18/24 M A C H 2 3 1 S P - 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS In-System Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • JTAG-Compatible, 5-V in-system programming ■ 100 Pins ■ Peripheral Component Interconnect PCI

Contextual Info: FIN AL M A C H 1 1 1 COM’L: -5/7.5/10/12/15/20 IND: -7.5/10/12/14/18/24 AM D£t F a m ily High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Programmable power-down mode ■ 32 Macrocells ■ 32 Outputs ■ 5 ns tPD ■ 32 Flip-flops; 4 clock choices

Contextual Info: FINAL COM’L : -7/10/12/15 IN D :-10/12/14/18 MACH 4-64/MACH4LV-64 B E Y O N D P E R FO R M A N C E High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 pins in PLCC, 44 and 48 pins in TQFP

Contextual Info: FIN A L COM'L: -10/12/15 IND:-12/14/18 MACH4-256/MACH4LV-256 V A N A IM T A M D I S High-Performance EE CMOS Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ 208 pins in PQFP 256 macrocells 10 ns t PD Commercial, 12 ns tPD Industrial

Contextual Info: FINAL V AN " V A N A M D C O M 'L : - 5 /7 /1 0 /1 2 /1 5 I N D : -7 /1 0 /1 2 /1 4 /1 8 M ACH131SP-5/7/10/1 i n 5 T I S High-Performance EE CMOS In-System Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Contextual Info: FINAL COM'L: -6/7 /10/12/15 IN D :-12/14/18 M A C H 2 3 1 -6 /7 /1 0 /1 2 /1 5 V A N A N A M D T I S High-Performance EE CMOS Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 84 Pins in PLCC 128 Macrocells

Contextual Info: FINAL BEYOND PERFORMANCE COM’L: -7/10/12/15 IND: -10/12/14/18 MACH 4-128N/MACH4LV-128N High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 84-pins in PLCC 128 macrocells

tico 732

Abstract: 5B12 DT114 tms 3755 5B7 Marking LV 20-P 5a7 02 ALL-07 PROGRAMMER
Contextual Info: PRELIMINARY COM’L: -7/10/12/15 IND: -10/12/15/20 The MACH5-384/MACH5LV-384 MACH5-384/120-7/10/12/15/20 MACH5-384/160-7/10/12/15/20 MACH5-384/184-7/10/12/15/20 MACH5-384/192-7/10/12/15/20 MACH5LV-384/120-7/10/12/15/20 MACH5LV-384/160-7/10/12/15/20 MACH5LV-384/184-7/10/12/15/20 MACH5LV-384/192-7/10/12/15/20

O-81-4

Abstract: MACH211SP MACH110 MACH111SP PALCE22V10 MACH111SP-10JC PALCE* programming
Contextual Info: FINAL COM’L: -5/7.5/10/12/15 IND: -7.5/10/12/14/18 MACH111SP-5/7/10/12/15 High-Density EE CMOS Programmable Logic V A N T I S The Programmable Logic Company From AMD DISTINCTIVE CHARACTERISTICS • JTAG-Compatible, 5-V in-system programming ■ Programmable power-down mode

MACH120

Abstract: mach 3 family amd AMD Graphics schematics PAL26V12 mach 1 to 5 from amd mach 1 family amd teradyne lasar MACH220 PAL22V10 mach schematic
Contextual Info: FINAL COM’L: -12/15/20 IND: -18/24 Advanced Micro Devices MACH120-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 56 Inputs 48 Macrocells 48 Outputs 12 ns tPD Commercial 18 ns tPD Industrial 48 Flip-flops; 4 clock choices