R10DS0098EJ0100 Search Results

Contextual Info: Datasheet PD48288109A μPD48288118A R10DS0098EJ0100 Rev.1.00 February 28, 2012 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288109A is a 33,554,432-word by 9 bit and the μPD48288118A is a 16,777,216-word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.