RDQS15 Search Results

MT9HVF12872PZ

Abstract: sdram ddr2
Contextual Info: 1GB x72, ECC, SR 240-Pin DDR2 SDRAM VLP RDIMM Features DDR2 SDRAM VLP RDIMM MT9HVF12872PZ – 1GB Features Figure 1: 240-Pin RDIMM (ATCA Form Factor) • 240-pin, registered very low profile, dual in-line memory module, ATCA form factor • Fast data transfer rates: PC2-3200, PC2-4200,

syscon

Abstract: LFEC1E-3T100C ips works 6CW3
Contextual Info: LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported

Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.7, September 2012 LatticeECP/EC Family Handbook Table of Contents September 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

Lattice Semiconductor Package Diagrams 256-Ball fpBGA

Abstract: 16-bit adder
Contextual Info: LatticeECP2/M Family Data Sheet DS1007 Version 02.1, September 2006 LatticeECP2/M Family Data Sheet Introduction September 2006 Advance Data Sheet DS1007 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic

prbs pattern generator using vhdl

Abstract: BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.9, April 2011 LatticeECP2/M Family Handbook Table of Contents April 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

LFEC6E-3T144C

Abstract: PT15B EC656
Contextual Info: LatticeECP/EC Family Data Sheet Version 02.2, March 2006 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported

lfe2

Abstract: PL25B
Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.6, April 2007 LatticeECP2/M Family Data Sheet Introduction April 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic

Catalog Toshiba

Abstract: st smd diode marking code G11 laser diode head toshiba semiconductor general catalog
Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.3, March 2010 LatticeECP/EC Family Handbook Table of Contents March 2010 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 02.2, February 2007 LatticeECP2/M Family Handbook Table of Contents February 2007 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

lfe2m35e7fn484c

Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.7, July 2007 LatticeECP2/M Family Data Sheet Introduction July 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic • Source synchronous standards support

Contextual Info: Rev: 102108 DS33M33 Demo Kit General Description The DS33M33 demo kit DK is an easy-to-use evaluation board for the DS33M33 and the DS33M33 Ethernet-over-SONET/SDH devices. The demo kit contains an option for either T3 or E3. The T3E3 links are complete with line interface, transformers, and

Contextual Info: Rev: 031008 Ge ne ra l De sc ript ion The DS33X162 demo kit DK is an easy-to-use evaluation board for the DS33X162 Ethernet-overPDH device. The demo kit contains an option for either T3/E3 or T1/E1 serial links. All serial links are complete with line interface, transformers, and

MT47H128M8

Contextual Info: 512MB, 1GB x72, ECC, SR 240-Pin DDR2 SDRAM VLP RDIMM Features DDR2 SDRAM VLP RDIMM MT9HVF6472PZ – 512MB MT9HVF12872PZ – 1GB Features Figure 1: 240-Pin RDIMM (ATCA Form Factor) • 240-pin, registered very low profile, dual in-line memory module, ATCA form factor

transistor a015 SMD

Abstract: IDT DATECODE MARKINGS A016 SMD smd diode marking A03 st smd diode marking code aa8 a012 SMD a013 SMD tqfp-208 fujitsu ten a015 SMD LFEC6E-5T144C
Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.1, February 2008 LatticeECP/EC Family Handbook Table of Contents February 2008 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

dp83484

Abstract: DP83848W RPB10 dp8348 CN1J4TTD 4pin xtal BDQS14 CB20 RB35 RB50
Contextual Info: Rev: 080508 DS33Z11 Demo Kit Features General Description The DS33Z11 demo kit is an easy-to-use evaluation board for the DS33Z11 Ethernet transport-over-serial link device. The DS33Z11DK contains an integrated Ethernet PHY and serial link. The serial link is

minidimm

Abstract: DDR2-400 DDR2-533 DDR2-667 PC2-3200 PC2-5300
Contextual Info: 1GB: x72, DR 244-Pin DDR2 VLP Reg. MiniDIMM Features DDR2 VLP Registered MiniDIMM MT18HVS12872(P)K – 1GB For component specifications, refer to Micron’s Web site: www.micron.com/products/ddr2sdram Features Figure 1: • 244-pin, very low profile mini dual in-line memory

PT15B

Abstract: R8K10 DDR400 LFEC10 LFEC15 LFEC33 LFECP10 LFECP15 LFECP20 LFECP33
Contextual Info: LatticeECP/EC Family Data Sheet Version 02.2, March 2006 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported

Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.8, November 2012 LatticeECP/EC Family Handbook Table of Contents November 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

LFEC6E-5T144C

Abstract: PB18A BDQS14 flip flop T Toggle pl25a 5qn208c PB20A LFEC6E-4FN256C PB11B PL18B
Contextual Info: LatticeECP/EC Family Data Sheet DS1000 Version 02.7, February 2008 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported

LFEC1E-3Tn100C

Abstract: DDR400 LFEC10 LFEC15 LFEC33 LFECP10 LFECP15 LFECP20 LFECP33 LFEC1E-3TN144I
Contextual Info: LatticeECP/EC Family Data Sheet Version 01.4, December 2004 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os

Contextual Info: LatticeECP/EC Family Handbook Version 02.7, January 2007 LatticeECP/EC Family Handbook Table of Contents January 2007 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

QD004

Abstract: BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 03.5, February 2008 LatticeECP2/M Family Handbook Table of Contents February 2008 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

sgmii switch

Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 03.5, November 2009 LatticeECP2/M Family Data Sheet Introduction June 2008 Data Sheet DS1006 Features Pre-Engineered Source Synchronous I/O • DDR registers in I/O cells • Dedicated gearing logic • Source synchronous standards support

Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 03.0, February 2008 LatticeECP2/M Family Data Sheet Introduction August 2007 Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic • Source synchronous standards support