S0095 Search Results

Contextual Info: TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP www.ti.com. SGLS314D – JUNE 2006 – REVISED MAY 2008

Contextual Info: I R C H I L D S E M I C O N D U C T O R TM 74F545 Octal Bidirectional Transceiver with 3-STATE Outputs General Description Features The ’ F545 is an 8-bit, 3-STATE, high-speed transceiver. It provides bidirectional drive fo r bus-oriented m icroprocessor

1114-3 data transceiver

Contextual Info: S E M IC O N D U C T O R -n 74F245 Octal Bidirectional Transceiver with 3-STATE Outputs General Description Features The ’ F245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented appli­ cations. Current sinking capability is 24 mA 20 mA Mil at

Scans-051

Contextual Info: C H IL D S E M I C O N D U C T O R TM 74F378 Parallel D Register with Enable General Description The ’F378 is a 6-bit register with a buffered common Enable. This device is similar to the ’F174, but with common Enable rather than common Master Reset. •

Contextual Info: S E M IC O N D U C T O R 74F243 Quad Bus Transceiver w ith 3-STATE O utputs General Description The ’ F243 is a quad bus transmitter/receiver designed for 4-line asynchronous 2-way data communications between data busses. Input clamp diodes limit high-speed termination effects

Contextual Info: S E M IC O N D U C T O R tm 74F564 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ’ F564 is a high-speed, low pow er octal flip-flop with a buffered com m on C lock CP and a buffered com m on O ut­ put Enable (OE). The inform ation presented to the D inputs

Contextual Info: S E M IC O N D U C T O R tm 74F379 Quad Parallel Register with Enable General Description The F379 is a 4-bit register w ith buffered com m on Enable. This device Is sim ilar to t h e ’F175 but features the com m on Enable rather than com m on M aster Reset.

1G51

Contextual Info: S E M IC O N D U C T O R 74F257A Quad 2-Input M ultiplexer w ith 3-STATE O utputs General Description Features The ’ F257A is a quad 2-input multiplexer with 3-STATE out­ puts. Four bits of data from two sources can be selected us­ ing a Common Data Select input. The four outputs present

Contextual Info: S E M IC O N D U C T O R 74F352 Dual 4-Input M ultiplexer General Description Features The ’F352 is a very high-speed dual 4-input multiplexer with common Select inputs and individual Enable inputs tor each section. It can select two bits ot data trom tour sources. The

3bs3

Contextual Info: S E M I C O N D U C T O R TM 74F537 1-of-10 Decoder with 3-STATE Outputs General Description o u tp u ts to th e h ig h im p e d a n c e s ta te . T w o in p u t e n a b le s , a c ­ tiv e H IG H E 2 a n d a c tiv e L O W E 1 a re a v a ila b le fo r d e m u lti­

Contextual Info: S E M IC O N D U C T O R 74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins General Description Features The ’F323 is an 8-bit universal shill/storage register with 3-STATE outputs. Its tunction is similar to the ’F299 with the

Contextual Info: S E M IC O N D U C T O R tm 74F381 4-Bit Arithmetic Logic Unit General Description Features The ’F381 perform s three a rithm etic and three logic ope ra ­ tions on tw o 4-bit w ords, A and B. Tw o additional select input codes force th e function outputs LOW o r HIGH. C arry propa­

Contextual Info: R C H II_ D S E M IC O N D U C T O R tm 74F377 Octal D Flip-Flop with Clock Enable G en eral D escrip tio n F e a tu re s The ’F377 has eight edge-triggered, D-type flip-flops w ith in­ dividual D inputs and Q outputs. The com m on buffered C lock CP input loads all flip-flops sim ultaneously, w hen the Clock

1SCA022

Abstract: OESA630DV12PL oesa 630 OS25F1210 1SCA022434R7810 OS160D 1SCC311006C0201 OS125D OESA630D3PL 1SCA022716R0180
Contextual Info: Low Voltage Products Fusegear, PowerLine switch fuses OS and OESA Switch fuses 16.80 DIN AC23/400V OS16D OS35D 7.5 kW 15 kW OS40D 15 kW OS32D OS63D 18.5 kW 15 kW OS125D OS160D 30 kW 55 kW OS200D 75 kW OS250D 110 kW BS AC23/415V OS20B OS32B 7.5 kW 15 kW OS32B OS63B

Contextual Info: S E M IC O N D U C T O R tm 74F521 8-Bit Identity Comparator General Description Features The ’ F521 is an expandable 8-bit com parator. It com pares tw o w ords of up to e ight bits each and provides a LOW o ut­ put w hen th e tw o w ords match bit fo r bit. The expansion in­

Contextual Info: D P n l 1 9 H8 M QQQ Revised Marchh i1999 SEMICONDUCTOR TM 74F543 Octal Registered Transceiver General Description Features T h e F543 octal tra n sce ive r contains tw o sets of D-type latches fo r tem porary storage of d ata flow ing in either direction. S eparate Latch Enable and O utput Enable inputs

55B8

Abstract: 00160A 74F280
Contextual Info: S E M IC O N D U C T O R 74F280 9-Bit Parity G enerator/C hecker General Description Features The ’ F280 is a high-speed parity generator/checker that ac­ cepts nine bits ot input data and detects whether an even or an odd number ot these inputs is HIGH. It an even number ot

Contextual Info: TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP www.ti.com SGLS314C – JUNE 2006 – REVISED AUGUST 2006 FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN FEATURES • TLV4112 D OR DGN PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication

ti 1974

Contextual Info: TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP www.ti.com SGLS314B – JUNE 2006 – REVISED AUGUST 2006 FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN FEATURES • TLV4112 D OR DGN PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication

Contextual Info: S E M IC O N D U C T O R 74F2243 Quad Bus Transceiver with 25Q Series Resistors in the Outputs General Description Features The ’F2243 is a quad bus tra nsm itter/receiver w hich can be used lo r 4-line a synchronous 2-w ay d a ta com m unications between data busses. It is designed to drive the capacitive

S009595

Contextual Info: S E M IC O N D U C T O R 74F821 10-Bit D-Type Flip-Flop General Description Features The ’ F821 is a 10-bit D-type Hip-Hop with 3-STATE true out­ puts arranged in a broadside pinout. The ’F821 is function­ ally and pin compatible with the AMD’s Am29821.

Contextual Info: S E M IC O N D U C T O R 74F827 • 74F828 10-Bit Buffers/Line Drivers General Description Features The ’ F827 and ’F828 10-bit bus buffers provide high perfor­ mance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output

Contextual Info: S E M IC O N D U C T O R -n 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all

Contextual Info: S E M IC O N D U C T O R 74F841 10-Bit Transparent Latch General Description The ’F841 bus interface latch is designed to eliminate the ex­ tra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carry­