SN54LV125 Search Results

LV125A

Abstract: 74lv125a A115-A C101 SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124F – DECEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A 74LV125
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124J – DECEMBER 1997 – REVISED JULY 2003 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A 6

LV125A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124I – DECEMBER 1997 – REVISED OCTOBER 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124I – DECEMBER 1997 – REVISED OCTOBER 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A

A115-A

Abstract: C101 LV125A SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

LV125A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124A - DECEMBER 1997 - REVISED MARCH 1998 EPICM Enhanced-Performance Implanted CMOS Process SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)

A115-A

Abstract: C101 LV125A SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

LV125A

Abstract: SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124D – DECEMBER 1997 – REVISED JULY 1998 D D D D D EPIC Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

LV125

Abstract: SN54LV125 SN74LV125 SN74LV125D SN74LV125DBLE SN74LV125DR SN74LV125PWLE
Contextual Info: SN54LV125, SN74LV125 QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124C - DECEMBER 1997 - REVISED MAY 1998 EPIC * Enhanced-Performance Implanted CMOS Process SN54LV125A . . . J O f i W PACKAGE SN74L.V125A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D Ioff Supports Partial-Power-Down Mode D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124I – DECEMBER 1997 – REVISED OCTOBER 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A 74LV125a
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

Contextual Info: SN54LV125, SN74LV125 QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES003B − NOVEMBER 1994 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 LV125A SN54LV125A SN74LV125A SN74LV125AN
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124K − DECEMBER 1997 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124D – DECEMBER 1997 – REVISED JULY 1998 D EPIC Enhanced-Performance Implanted D D D D CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

LV125

Abstract: SN54LV125 SN74LV125 SN74LV125D SN74LV125DBLE SN74LV125DR SN74LV125PWLE
Contextual Info: SN54LV125, SN74LV125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES003B – NOVEMBER 1994 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A