SN7427 Search Results

IC 74273

Abstract: 74L8273 SNS4LS273 SN74LS273 V ls273
Contextual Info: TYPES SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR TTL MSI B U L L E T I N N O . O L-S 7 S 1 2 0 9 1 . O C T O B E R 1976 Contains Eight Ffip-Flops with Single-Rail Outputs SN M 273. SN B4LS273. . . J PA C KA G E SN74273. SN74LS273 . . . J OR N PA C KA G E

74278

Contextual Info: TYPES SN54278, SN74278 4-BIT CASCADABLE PRIORITY REGISTERS M AY 1 972 —R E V ISE D A P R IL 1 98 5 Latched Data Inputs Serve as Buffer Register and Can also: Synchronize Data Acquisition "Debounce" Mechanical Switch Input • Cascading Input PO and Output P1

AS 15 -g

Abstract: LW2J
Contextual Info: TYPES SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS O C T O B E R 1 9 7 6 — R E V IS E D D E C E M B E R 1 9 8 3 features • Four J-K Flip-Flops in a Single Package . . . Can Reduce FF Package Count by 50% • Separate Negative-Edge-Triggered Clocks with Hysteresis , . . Typically 200 mV

logic diagram of ic 7427

Contextual Info: TYPES SN5427, SN54LS27, SN7427. SN74LS27 TRIPLE 3-INPUT POSITIVE-NOR GATES R E V ISE D D EC EM B ER 1983 Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs S N 5 4 2 7 . S N 5 4 L S 2 7 . . J O R W P A C K A G E

74273n

Abstract: 74LS273
Contextual Info: TYPES SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR O CTO BER 1976 • Contains Eight Flip-Flops w ith Single-Rail Outputs • Buffered Clock and D irect Clear Inputs . . J PACKAGE S N 7 4 2 7 3 . . . J OR N PACKAGE S N 7 4 L S 2 7 3 . . . D W , J OR N PACKAGE

74LS273

Abstract: LS273 SN54273 SN54LS273 SN74273 SN74LS273
Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop

Contextual Info: SN54279, SN54LS279A, SN74279, SN74LS279A QUADRUPLE S-R LATCHES SDLS093 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

Contextual Info: SN54279, SN54LS279A, SN74279, SN74LS279A QUADRUPLE S-R LATCHES SDLS093 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

LS273

Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

SN5427

Abstract: SN7427 ScansUX1020
Contextual Info: CIRCUIT TYPES SN5427, SN7427 TRIPLE 3-INPUT POSITIVE-NOR GATES J O R N D U A L - IN - L IN E O R W F L A T P A C K A G E T O P V IE W * schematic (each gate) VCC 1C 1Y 3C 3B 3A 3Y positive logic: Y = A + B + C C o m p o n e n t valu es sh o w n are n o m in a l.

LS279A

Abstract: SN54279 SN54LS279A SN74 SN74279 SN74LS279A
Contextual Info: TYPES SN54279, SN54LS279A, SN74279l SN74LS279A QUADRUPLE S-R LATCHES R E V IS E D D E C E M B E R 1 9 8 3 Package O ptions Include Both Plastic and Ceram ic Chip Carriers in A d dition to Plastic and Ceramic DIPs S N 5427 9, SN 54LS 279A . . . J OR W PACKAGE

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

ls273

Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop

ls273

Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop

SN74LS273 V

Abstract: SNJ54LS273J SNJ54LS273 ls273 SN54LS273J
Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop

SN74LS273

Abstract: LS273 SN54273 SN54LS273 SN74273 SN74LS273DWR SN74LS273NSR
Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • • • • Contains Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop

7601801EA

Abstract: 7601801FA SN54279 SN54279J SN54LS279A SN54LS279AJ SN74279 SN74279N SN74LS279A
Contextual Info: SN54279, SN54LS279A, SN74279, SN74LS279A QUADRUPLE S-R LATCHES SDLS093 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D TYPE FLIP-FLOP WITH CLEAR OCTOBER 1976 - REVISED MARCH 1988 S N 5 4 2 7 3 , S N 7 4 L S 2 7 3 . . . J OR W P A C K A G E Contains Eight Flip-Flops with Single-Rail Outputs SN 74273 . . . N PACKAG E S N 7 4 L S 2 7 3 . . . DW OR N P A C K A G E

SN74LS27

Abstract: SN7427 kd 617 TTL SN7427 LS27 SN5427 SN54LS27 SN74
Contextual Info: | SN5427, SN 54LS27, SN7427, SN 74LS27 TRIPLE 3 INPUT POSITIVENOR GATES SDLS089 DECEMBER 1 9 8 3 -R E V IS E D M A H C H 1 3 8 8 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

Contextual Info: SN54279, SN54LS279A, SN74279, SN74LS279A QUADRUPLE S-R LATCHES SDLS093 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN74273N IL00 * TTL OCTAL D-TYPE FLIP-FLOPS WITH DIRECT RESET –TOP VIEW– Q8 19 20 VCC D8 18 D7 17 Q7 16 D6 14 Q6 15 D5 13 Q5 12 CK 11 3 4 +5V 7 8 13 14 17 GND 10 1 2 3 4 5 6 7 8 9 RD Q1 D1 D2 Q2 Q3 D3 D4 Q4 18 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6

Contextual Info: SN54279, SN54LS279A, SN74279, SN74LS279A QUADRUPLE S-R LATCHES SDLS093 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments