SN74ALVC08 Search Results

VA08

Abstract: SN74ALVC08 SN74ALVC08D SN74ALVC08RGYR A115-A C101
Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101G – JULY 1997 – REVISED JULY 2003 1A 1B 1Y 2A 2B 2Y GND description/ordering information 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y RGY PACKAGE TOP VIEW This quadruple 2-input positive-AND gate is

Contextual Info: SN74ALVC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES522A − DECEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification

A115-A

Abstract: C101 SN74ALVC08 SN74ALVC08D SN74ALVC08RGYR
Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

SN74ALVC08

Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101D – JULY 1997 – REVISED AUGUST 1998 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

va08

Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

SN74ALVC08

Abstract: SN74ALVC08D SN74ALVC08RGYR A115-A C101
Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

Contextual Info: SN74ALVC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES522A − DECEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification

Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

Contextual Info: SN74ALVC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES491C − SEPTEMBER 2003 − REVISED JANUARY 2008 D OR PW PACKAGE TOP VIEW D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74ALVC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES491C − SEPTEMBER 2003 − REVISED JANUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D OR PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74ALVC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES491C − SEPTEMBER 2003 − REVISED JANUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D OR PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

Contextual Info: Contents Page ALVC Gates/Octals SN74ALVC00 SN74ALVC04 SN74ALVC08 SN74ALVC10 SN74ALVC14 SN74ALVC32 SN74ALVC74 SN74ALVC125 SN74ALVC126 SN74ALVC244 SN74ALVCH244 SN74ALVC245 SN74ALVCH245 SN74ALVCH373 SN74ALVCH374 2–2 Quadruple 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contextual Info: SN74ALVC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES522A − DECEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification

Contextual Info: SN74ALVC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES522A − DECEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification

Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

Contextual Info: SN74ALVC08ĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES491C − SEPTEMBER 2003 − REVISED JANUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D OR PW PACKAGE TOP VIEW MIL-STD-883, Method 3015; Exceeds 200 V

Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

A115-A

Abstract: SN74ALVC08 SN74ALVC08D SN74ALVC08DR SN74ALVC08NSR SN74ALVC08PWR
Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101E – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A)

VA08

Abstract: A115-A SN74ALVC08 SN74ALVC08D SN74ALVC08DR SN74ALVC08NSR SN74ALVC08RGYR
Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101F – JULY 1997 – REVISED SEPTEMBER 2002 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.9 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

Contextual Info: SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

Contextual Info: SN74ALVC08ĆQ1 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES491B − SEPTEMBER 2003 − REVISED MAY 2004 D Qualification in Accordance With D D D D D D D Latch-Up Performance Exceeds 250 mA Per AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control

Contextual Info: SN74ALVC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES522A − DECEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification

Contextual Info: SN74ALVC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCES522A − DECEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification